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path: root/drivers/pinctrl
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-rw-r--r--drivers/pinctrl/nxp/Kconfig6
-rw-r--r--drivers/pinctrl/nxp/Makefile2
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx.h8
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx8m.c62
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx8mm.c310
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx8mn.c310
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx8mp.c309
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx8mq.c310
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx9.c89
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx91.c228
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx93.c244
11 files changed, 1849 insertions, 29 deletions
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 84d9a3641ff..b2a19557a27 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -103,13 +103,13 @@ config PINCTRL_IMX8M
registers.
config PINCTRL_IMX93
- bool "IMX8M pinctrl driver"
+ bool "IMX93/1 pinctrl driver"
depends on ARCH_IMX9 && PINCTRL_FULL
select PINCTRL_IMX_MMIO
help
- Say Y here to enable the imx8m pinctrl driver
+ Say Y here to enable the imx9[3,1] pinctrl driver
- This provides a simple pinctrl driver for i.MX8M SoC familiy.
+ This provides a simple pinctrl driver for i.MX9[3,1] SoC.
This feature depends on device tree configuration. This driver
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configure related
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index 7d861ae52c1..7f1cc5a182f 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -7,7 +7,7 @@ obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o
-obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o
+obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx9.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h
index 9adf999d3bb..569bb869abd 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.h
+++ b/drivers/pinctrl/nxp/pinctrl-imx.h
@@ -6,6 +6,14 @@
#ifndef __DRIVERS_PINCTRL_IMX_H
#define __DRIVERS_PINCTRL_IMX_H
+#define PINCTRL_PIN(a, b) { .number = a, .name = b }
+#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+struct imx_pinctrl_pin_desc {
+ unsigned int number;
+ const char *name;
+};
+
/**
* @base: the address to the controller in virtual memory
* @input_sel_base: the address of the select input in virtual memory.
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c
index d9c63b3aca6..6eec1a277b3 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8m.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c
@@ -4,21 +4,83 @@
*/
#include <dm/device.h>
+#include <dm/device_compat.h>
#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <asm/io.h>
#include "pinctrl-imx.h"
static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info __section(".data");
static const struct udevice_id imx8m_pinctrl_match[] = {
+#if IS_ENABLED(CONFIG_IMX8MQ)
{ .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
+#endif
+#if IS_ENABLED(CONFIG_IMX8MM)
{ .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
+#endif
+#if IS_ENABLED(CONFIG_IMX8MN)
{ .compatible = "fsl,imx8mn-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
+#endif
+#if IS_ENABLED(CONFIG_IMX8MP)
{ .compatible = "fsl,imx8mp-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
+#endif
{ /* sentinel */ }
};
+#if CONFIG_IS_ENABLED(CMD_PINMUX)
+
+#if IS_ENABLED(CONFIG_IMX8MP)
+#include "pinctrl-imx8mp.c"
+#elif IS_ENABLED(CONFIG_IMX8MN)
+#include "pinctrl-imx8mn.c"
+#elif IS_ENABLED(CONFIG_IMX8MM)
+#include "pinctrl-imx8mm.c"
+#elif IS_ENABLED(CONFIG_IMX8MQ)
+#include "pinctrl-imx8mq.c"
+#endif
+
+static int imx8m_get_pins_count(struct udevice *dev)
+{
+ return ARRAY_SIZE(imx8m_pinctrl_pads);
+}
+
+static const char *imx8m_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ /* sanity checking */
+ if (selector != imx8m_pinctrl_pads[selector].number) {
+ dev_err(dev,
+ "selector(%u) not match with imx8m_pinctrl_pads[selector].number(%u)\n",
+ selector, imx8m_pinctrl_pads[selector].number);
+ return NULL;
+ }
+
+ return imx8m_pinctrl_pads[selector].name;
+}
+
+static int imx8m_get_pin_muxing(struct udevice *dev, unsigned int selector,
+ char *buf, int size)
+{
+ struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+ struct imx_pinctrl_soc_info *info = priv->info;
+ u32 mux_reg = selector << 2;
+ u32 mux_mode = readl(info->base + mux_reg);
+
+ snprintf(buf, size, "Function(%d) at: 0x%p", mux_mode & 0x7, info->base + mux_reg);
+
+ return 0;
+}
+#endif
+
static const struct pinctrl_ops imx8m_pinctrl_ops = {
+#if CONFIG_IS_ENABLED(CMD_PINMUX)
+ .get_pin_name = imx8m_get_pin_name,
+ .get_pins_count = imx8m_get_pins_count,
+ .get_pin_muxing = imx8m_get_pin_muxing,
+#endif
.set_state = imx_pinctrl_set_state_mmio,
};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mm.c b/drivers/pinctrl/nxp/pinctrl-imx8mm.c
new file mode 100644
index 00000000000..9aa2303b618
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx8mm.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "pinctrl-imx.h"
+
+enum imx8mm_pads {
+ RESERVE0 = 0,
+ RESERVE1 = 1,
+ RESERVE2 = 2,
+ RESERVE3 = 3,
+ RESERVE4 = 4,
+ RESERVE5 = 5,
+ RESERVE6 = 6,
+ RESERVE7 = 7,
+ RESERVE8 = 8,
+ RESERVE9 = 9,
+ GPIO1_IO00 = 10,
+ GPIO1_IO01 = 11,
+ GPIO1_IO02 = 12,
+ GPIO1_IO03 = 13,
+ GPIO1_IO04 = 14,
+ GPIO1_IO05 = 15,
+ GPIO1_IO06 = 16,
+ GPIO1_IO07 = 17,
+ GPIO1_IO08 = 18,
+ GPIO1_IO09 = 19,
+ GPIO1_IO10 = 20,
+ GPIO1_IO11 = 21,
+ GPIO1_IO12 = 22,
+ GPIO1_IO13 = 23,
+ GPIO1_IO14 = 24,
+ GPIO1_IO15 = 25,
+ ENET_MDC = 26,
+ ENET_MDIO = 27,
+ ENET_TD3 = 28,
+ ENET_TD2 = 29,
+ ENET_TD1 = 30,
+ ENET_TD0 = 31,
+ ENET_TX_CTL = 32,
+ ENET_TXC = 33,
+ ENET_RX_CTL = 34,
+ ENET_RXC = 35,
+ ENET_RD0 = 36,
+ ENET_RD1 = 37,
+ ENET_RD2 = 38,
+ ENET_RD3 = 39,
+ SD1_CLK = 40,
+ SD1_CMD = 41,
+ SD1_DATA0 = 42,
+ SD1_DATA1 = 43,
+ SD1_DATA2 = 44,
+ SD1_DATA3 = 45,
+ SD1_DATA4 = 46,
+ SD1_DATA5 = 47,
+ SD1_DATA6 = 48,
+ SD1_DATA7 = 49,
+ SD1_RESET_B = 50,
+ SD1_STROBE = 51,
+ SD2_CD_B = 52,
+ SD2_CLK = 53,
+ SD2_CMD = 54,
+ SD2_DATA0 = 55,
+ SD2_DATA1 = 56,
+ SD2_DATA2 = 57,
+ SD2_DATA3 = 58,
+ SD2_RESET_B = 59,
+ SD2_WP = 60,
+ NAND_ALE = 61,
+ NAND_CE0 = 62,
+ NAND_CE1 = 63,
+ NAND_CE2 = 64,
+ NAND_CE3 = 65,
+ NAND_CLE = 66,
+ NAND_DATA00 = 67,
+ NAND_DATA01 = 68,
+ NAND_DATA02 = 69,
+ NAND_DATA03 = 70,
+ NAND_DATA04 = 71,
+ NAND_DATA05 = 72,
+ NAND_DATA06 = 73,
+ NAND_DATA07 = 74,
+ NAND_DQS = 75,
+ NAND_RE_B = 76,
+ NAND_READY_B = 77,
+ NAND_WE_B = 78,
+ NAND_WP_B = 79,
+ SAI5_RXFS = 80,
+ SAI5_RXC = 81,
+ SAI5_RXD0 = 82,
+ SAI5_RXD1 = 83,
+ SAI5_RXD2 = 84,
+ SAI5_RXD3 = 85,
+ SAI5_MCLK = 86,
+ SAI1_RXFS = 87,
+ SAI1_RXC = 88,
+ SAI1_RXD0 = 89,
+ SAI1_RXD1 = 90,
+ SAI1_RXD2 = 91,
+ SAI1_RXD3 = 92,
+ SAI1_RXD4 = 93,
+ SAI1_RXD5 = 94,
+ SAI1_RXD6 = 95,
+ SAI1_RXD7 = 96,
+ SAI1_TXFS = 97,
+ SAI1_TXC = 98,
+ SAI1_TXD0 = 99,
+ SAI1_TXD1 = 100,
+ SAI1_TXD2 = 101,
+ SAI1_TXD3 = 102,
+ SAI1_TXD4 = 103,
+ SAI1_TXD5 = 104,
+ SAI1_TXD6 = 105,
+ SAI1_TXD7 = 106,
+ SAI1_MCLK = 107,
+ SAI2_RXFS = 108,
+ SAI2_RXC = 109,
+ SAI2_RXD0 = 110,
+ SAI2_TXFS = 111,
+ SAI2_TXC = 112,
+ SAI2_TXD0 = 113,
+ SAI2_MCLK = 114,
+ SAI3_RXFS = 115,
+ SAI3_RXC = 116,
+ SAI3_RXD = 117,
+ SAI3_TXFS = 118,
+ SAI3_TXC = 119,
+ SAI3_TXD = 120,
+ SAI3_MCLK = 121,
+ SPDIF_TX = 122,
+ SPDIF_RX = 123,
+ SPDIF_EXT_CLK = 124,
+ ECSPI1_SCLK = 125,
+ ECSPI1_MOSI = 126,
+ ECSPI1_MISO = 127,
+ ECSPI1_SS0 = 128,
+ ECSPI2_SCLK = 129,
+ ECSPI2_MOSI = 130,
+ ECSPI2_MISO = 131,
+ ECSPI2_SS0 = 132,
+ I2C1_SCL = 133,
+ I2C1_SDA = 134,
+ I2C2_SCL = 135,
+ I2C2_SDA = 136,
+ I2C3_SCL = 137,
+ I2C3_SDA = 138,
+ I2C4_SCL = 139,
+ I2C4_SDA = 140,
+ UART1_RXD = 141,
+ UART1_TXD = 142,
+ UART2_RXD = 143,
+ UART2_TXD = 144,
+ UART3_RXD = 145,
+ UART3_TXD = 146,
+ UART4_RXD = 147,
+ UART4_TXD = 148,
+};
+
+static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(RESERVE0),
+ IMX_PINCTRL_PIN(RESERVE1),
+ IMX_PINCTRL_PIN(RESERVE2),
+ IMX_PINCTRL_PIN(RESERVE3),
+ IMX_PINCTRL_PIN(RESERVE4),
+ IMX_PINCTRL_PIN(RESERVE5),
+ IMX_PINCTRL_PIN(RESERVE6),
+ IMX_PINCTRL_PIN(RESERVE7),
+ IMX_PINCTRL_PIN(RESERVE8),
+ IMX_PINCTRL_PIN(RESERVE9),
+ IMX_PINCTRL_PIN(GPIO1_IO00),
+ IMX_PINCTRL_PIN(GPIO1_IO01),
+ IMX_PINCTRL_PIN(GPIO1_IO02),
+ IMX_PINCTRL_PIN(GPIO1_IO03),
+ IMX_PINCTRL_PIN(GPIO1_IO04),
+ IMX_PINCTRL_PIN(GPIO1_IO05),
+ IMX_PINCTRL_PIN(GPIO1_IO06),
+ IMX_PINCTRL_PIN(GPIO1_IO07),
+ IMX_PINCTRL_PIN(GPIO1_IO08),
+ IMX_PINCTRL_PIN(GPIO1_IO09),
+ IMX_PINCTRL_PIN(GPIO1_IO10),
+ IMX_PINCTRL_PIN(GPIO1_IO11),
+ IMX_PINCTRL_PIN(GPIO1_IO12),
+ IMX_PINCTRL_PIN(GPIO1_IO13),
+ IMX_PINCTRL_PIN(GPIO1_IO14),
+ IMX_PINCTRL_PIN(GPIO1_IO15),
+ IMX_PINCTRL_PIN(ENET_MDC),
+ IMX_PINCTRL_PIN(ENET_MDIO),
+ IMX_PINCTRL_PIN(ENET_TD3),
+ IMX_PINCTRL_PIN(ENET_TD2),
+ IMX_PINCTRL_PIN(ENET_TD1),
+ IMX_PINCTRL_PIN(ENET_TD0),
+ IMX_PINCTRL_PIN(ENET_TX_CTL),
+ IMX_PINCTRL_PIN(ENET_TXC),
+ IMX_PINCTRL_PIN(ENET_RX_CTL),
+ IMX_PINCTRL_PIN(ENET_RXC),
+ IMX_PINCTRL_PIN(ENET_RD0),
+ IMX_PINCTRL_PIN(ENET_RD1),
+ IMX_PINCTRL_PIN(ENET_RD2),
+ IMX_PINCTRL_PIN(ENET_RD3),
+ IMX_PINCTRL_PIN(SD1_CLK),
+ IMX_PINCTRL_PIN(SD1_CMD),
+ IMX_PINCTRL_PIN(SD1_DATA0),
+ IMX_PINCTRL_PIN(SD1_DATA1),
+ IMX_PINCTRL_PIN(SD1_DATA2),
+ IMX_PINCTRL_PIN(SD1_DATA3),
+ IMX_PINCTRL_PIN(SD1_DATA4),
+ IMX_PINCTRL_PIN(SD1_DATA5),
+ IMX_PINCTRL_PIN(SD1_DATA6),
+ IMX_PINCTRL_PIN(SD1_DATA7),
+ IMX_PINCTRL_PIN(SD1_RESET_B),
+ IMX_PINCTRL_PIN(SD1_STROBE),
+ IMX_PINCTRL_PIN(SD2_CD_B),
+ IMX_PINCTRL_PIN(SD2_CLK),
+ IMX_PINCTRL_PIN(SD2_CMD),
+ IMX_PINCTRL_PIN(SD2_DATA0),
+ IMX_PINCTRL_PIN(SD2_DATA1),
+ IMX_PINCTRL_PIN(SD2_DATA2),
+ IMX_PINCTRL_PIN(SD2_DATA3),
+ IMX_PINCTRL_PIN(SD2_RESET_B),
+ IMX_PINCTRL_PIN(SD2_WP),
+ IMX_PINCTRL_PIN(NAND_ALE),
+ IMX_PINCTRL_PIN(NAND_CE0),
+ IMX_PINCTRL_PIN(NAND_CE1),
+ IMX_PINCTRL_PIN(NAND_CE2),
+ IMX_PINCTRL_PIN(NAND_CE3),
+ IMX_PINCTRL_PIN(NAND_CLE),
+ IMX_PINCTRL_PIN(NAND_DATA00),
+ IMX_PINCTRL_PIN(NAND_DATA01),
+ IMX_PINCTRL_PIN(NAND_DATA02),
+ IMX_PINCTRL_PIN(NAND_DATA03),
+ IMX_PINCTRL_PIN(NAND_DATA04),
+ IMX_PINCTRL_PIN(NAND_DATA05),
+ IMX_PINCTRL_PIN(NAND_DATA06),
+ IMX_PINCTRL_PIN(NAND_DATA07),
+ IMX_PINCTRL_PIN(NAND_DQS),
+ IMX_PINCTRL_PIN(NAND_RE_B),
+ IMX_PINCTRL_PIN(NAND_READY_B),
+ IMX_PINCTRL_PIN(NAND_WE_B),
+ IMX_PINCTRL_PIN(NAND_WP_B),
+ IMX_PINCTRL_PIN(SAI5_RXFS),
+ IMX_PINCTRL_PIN(SAI5_RXC),
+ IMX_PINCTRL_PIN(SAI5_RXD0),
+ IMX_PINCTRL_PIN(SAI5_RXD1),
+ IMX_PINCTRL_PIN(SAI5_RXD2),
+ IMX_PINCTRL_PIN(SAI5_RXD3),
+ IMX_PINCTRL_PIN(SAI5_MCLK),
+ IMX_PINCTRL_PIN(SAI1_RXFS),
+ IMX_PINCTRL_PIN(SAI1_RXC),
+ IMX_PINCTRL_PIN(SAI1_RXD0),
+ IMX_PINCTRL_PIN(SAI1_RXD1),
+ IMX_PINCTRL_PIN(SAI1_RXD2),
+ IMX_PINCTRL_PIN(SAI1_RXD3),
+ IMX_PINCTRL_PIN(SAI1_RXD4),
+ IMX_PINCTRL_PIN(SAI1_RXD5),
+ IMX_PINCTRL_PIN(SAI1_RXD6),
+ IMX_PINCTRL_PIN(SAI1_RXD7),
+ IMX_PINCTRL_PIN(SAI1_TXFS),
+ IMX_PINCTRL_PIN(SAI1_TXC),
+ IMX_PINCTRL_PIN(SAI1_TXD0),
+ IMX_PINCTRL_PIN(SAI1_TXD1),
+ IMX_PINCTRL_PIN(SAI1_TXD2),
+ IMX_PINCTRL_PIN(SAI1_TXD3),
+ IMX_PINCTRL_PIN(SAI1_TXD4),
+ IMX_PINCTRL_PIN(SAI1_TXD5),
+ IMX_PINCTRL_PIN(SAI1_TXD6),
+ IMX_PINCTRL_PIN(SAI1_TXD7),
+ IMX_PINCTRL_PIN(SAI1_MCLK),
+ IMX_PINCTRL_PIN(SAI2_RXFS),
+ IMX_PINCTRL_PIN(SAI2_RXC),
+ IMX_PINCTRL_PIN(SAI2_RXD0),
+ IMX_PINCTRL_PIN(SAI2_TXFS),
+ IMX_PINCTRL_PIN(SAI2_TXC),
+ IMX_PINCTRL_PIN(SAI2_TXD0),
+ IMX_PINCTRL_PIN(SAI2_MCLK),
+ IMX_PINCTRL_PIN(SAI3_RXFS),
+ IMX_PINCTRL_PIN(SAI3_RXC),
+ IMX_PINCTRL_PIN(SAI3_RXD),
+ IMX_PINCTRL_PIN(SAI3_TXFS),
+ IMX_PINCTRL_PIN(SAI3_TXC),
+ IMX_PINCTRL_PIN(SAI3_TXD),
+ IMX_PINCTRL_PIN(SAI3_MCLK),
+ IMX_PINCTRL_PIN(SPDIF_TX),
+ IMX_PINCTRL_PIN(SPDIF_RX),
+ IMX_PINCTRL_PIN(SPDIF_EXT_CLK),
+ IMX_PINCTRL_PIN(ECSPI1_SCLK),
+ IMX_PINCTRL_PIN(ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(ECSPI1_MISO),
+ IMX_PINCTRL_PIN(ECSPI1_SS0),
+ IMX_PINCTRL_PIN(ECSPI2_SCLK),
+ IMX_PINCTRL_PIN(ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(ECSPI2_MISO),
+ IMX_PINCTRL_PIN(ECSPI2_SS0),
+ IMX_PINCTRL_PIN(I2C1_SCL),
+ IMX_PINCTRL_PIN(I2C1_SDA),
+ IMX_PINCTRL_PIN(I2C2_SCL),
+ IMX_PINCTRL_PIN(I2C2_SDA),
+ IMX_PINCTRL_PIN(I2C3_SCL),
+ IMX_PINCTRL_PIN(I2C3_SDA),
+ IMX_PINCTRL_PIN(I2C4_SCL),
+ IMX_PINCTRL_PIN(I2C4_SDA),
+ IMX_PINCTRL_PIN(UART1_RXD),
+ IMX_PINCTRL_PIN(UART1_TXD),
+ IMX_PINCTRL_PIN(UART2_RXD),
+ IMX_PINCTRL_PIN(UART2_TXD),
+ IMX_PINCTRL_PIN(UART3_RXD),
+ IMX_PINCTRL_PIN(UART3_TXD),
+ IMX_PINCTRL_PIN(UART4_RXD),
+ IMX_PINCTRL_PIN(UART4_TXD),
+};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mn.c b/drivers/pinctrl/nxp/pinctrl-imx8mn.c
new file mode 100644
index 00000000000..a3e22cf72ee
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx8mn.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "pinctrl-imx.h"
+
+enum imx8mn_pads {
+ RESERVE0 = 0,
+ RESERVE1 = 1,
+ RESERVE2 = 2,
+ RESERVE3 = 3,
+ RESERVE4 = 4,
+ RESERVE5 = 5,
+ RESERVE6 = 6,
+ RESERVE7 = 7,
+ BOOT_MODE2 = 8,
+ BOOT_MODE3 = 9,
+ GPIO1_IO00 = 10,
+ GPIO1_IO01 = 11,
+ GPIO1_IO02 = 12,
+ GPIO1_IO03 = 13,
+ GPIO1_IO04 = 14,
+ GPIO1_IO05 = 15,
+ GPIO1_IO06 = 16,
+ GPIO1_IO07 = 17,
+ GPIO1_IO08 = 18,
+ GPIO1_IO09 = 19,
+ GPIO1_IO10 = 20,
+ GPIO1_IO11 = 21,
+ GPIO1_IO12 = 22,
+ GPIO1_IO13 = 23,
+ GPIO1_IO14 = 24,
+ GPIO1_IO15 = 25,
+ ENET_MDC = 26,
+ ENET_MDIO = 27,
+ ENET_TD3 = 28,
+ ENET_TD2 = 29,
+ ENET_TD1 = 30,
+ ENET_TD0 = 31,
+ ENET_TX_CTL = 32,
+ ENET_TXC = 33,
+ ENET_RX_CTL = 34,
+ ENET_RXC = 35,
+ ENET_RD0 = 36,
+ ENET_RD1 = 37,
+ ENET_RD2 = 38,
+ ENET_RD3 = 39,
+ SD1_CLK = 40,
+ SD1_CMD = 41,
+ SD1_DATA0 = 42,
+ SD1_DATA1 = 43,
+ SD1_DATA2 = 44,
+ SD1_DATA3 = 45,
+ SD1_DATA4 = 46,
+ SD1_DATA5 = 47,
+ SD1_DATA6 = 48,
+ SD1_DATA7 = 49,
+ SD1_RESET_B = 50,
+ SD1_STROBE = 51,
+ SD2_CD_B = 52,
+ SD2_CLK = 53,
+ SD2_CMD = 54,
+ SD2_DATA0 = 55,
+ SD2_DATA1 = 56,
+ SD2_DATA2 = 57,
+ SD2_DATA3 = 58,
+ SD2_RESET_B = 59,
+ SD2_WP = 60,
+ NAND_ALE = 61,
+ NAND_CE0 = 62,
+ NAND_CE1 = 63,
+ NAND_CE2 = 64,
+ NAND_CE3 = 65,
+ NAND_CLE = 66,
+ NAND_DATA00 = 67,
+ NAND_DATA01 = 68,
+ NAND_DATA02 = 69,
+ NAND_DATA03 = 70,
+ NAND_DATA04 = 71,
+ NAND_DATA05 = 72,
+ NAND_DATA06 = 73,
+ NAND_DATA07 = 74,
+ NAND_DQS = 75,
+ NAND_RE_B = 76,
+ NAND_READY_B = 77,
+ NAND_WE_B = 78,
+ NAND_WP_B = 79,
+ SAI5_RXFS = 80,
+ SAI5_RXC = 81,
+ SAI5_RXD0 = 82,
+ SAI5_RXD1 = 83,
+ SAI5_RXD2 = 84,
+ SAI5_RXD3 = 85,
+ SAI5_MCLK = 86,
+ SAI1_RXFS = 87,
+ SAI1_RXC = 88,
+ SAI1_RXD0 = 89,
+ SAI1_RXD1 = 90,
+ SAI1_RXD2 = 91,
+ SAI1_RXD3 = 92,
+ SAI1_RXD4 = 93,
+ SAI1_RXD5 = 94,
+ SAI1_RXD6 = 95,
+ SAI1_RXD7 = 96,
+ SAI1_TXFS = 97,
+ SAI1_TXC = 98,
+ SAI1_TXD0 = 99,
+ SAI1_TXD1 = 100,
+ SAI1_TXD2 = 101,
+ SAI1_TXD3 = 102,
+ SAI1_TXD4 = 103,
+ SAI1_TXD5 = 104,
+ SAI1_TXD6 = 105,
+ SAI1_TXD7 = 106,
+ SAI1_MCLK = 107,
+ SAI2_RXFS = 108,
+ SAI2_RXC = 109,
+ SAI2_RXD0 = 110,
+ SAI2_TXFS = 111,
+ SAI2_TXC = 112,
+ SAI2_TXD0 = 113,
+ SAI2_MCLK = 114,
+ SAI3_RXFS = 115,
+ SAI3_RXC = 116,
+ SAI3_RXD = 117,
+ SAI3_TXFS = 118,
+ SAI3_TXC = 119,
+ SAI3_TXD = 120,
+ SAI3_MCLK = 121,
+ SPDIF_TX = 122,
+ SPDIF_RX = 123,
+ SPDIF_EXT_CLK = 124,
+ ECSPI1_SCLK = 125,
+ ECSPI1_MOSI = 126,
+ ECSPI1_MISO = 127,
+ ECSPI1_SS0 = 128,
+ ECSPI2_SCLK = 129,
+ ECSPI2_MOSI = 130,
+ ECSPI2_MISO = 131,
+ ECSPI2_SS0 = 132,
+ I2C1_SCL = 133,
+ I2C1_SDA = 134,
+ I2C2_SCL = 135,
+ I2C2_SDA = 136,
+ I2C3_SCL = 137,
+ I2C3_SDA = 138,
+ I2C4_SCL = 139,
+ I2C4_SDA = 140,
+ UART1_RXD = 141,
+ UART1_TXD = 142,
+ UART2_RXD = 143,
+ UART2_TXD = 144,
+ UART3_RXD = 145,
+ UART3_TXD = 146,
+ UART4_RXD = 147,
+ UART4_TXD = 148,
+};
+
+static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(RESERVE0),
+ IMX_PINCTRL_PIN(RESERVE1),
+ IMX_PINCTRL_PIN(RESERVE2),
+ IMX_PINCTRL_PIN(RESERVE3),
+ IMX_PINCTRL_PIN(RESERVE4),
+ IMX_PINCTRL_PIN(RESERVE5),
+ IMX_PINCTRL_PIN(RESERVE6),
+ IMX_PINCTRL_PIN(RESERVE7),
+ IMX_PINCTRL_PIN(BOOT_MODE2),
+ IMX_PINCTRL_PIN(BOOT_MODE3),
+ IMX_PINCTRL_PIN(GPIO1_IO00),
+ IMX_PINCTRL_PIN(GPIO1_IO01),
+ IMX_PINCTRL_PIN(GPIO1_IO02),
+ IMX_PINCTRL_PIN(GPIO1_IO03),
+ IMX_PINCTRL_PIN(GPIO1_IO04),
+ IMX_PINCTRL_PIN(GPIO1_IO05),
+ IMX_PINCTRL_PIN(GPIO1_IO06),
+ IMX_PINCTRL_PIN(GPIO1_IO07),
+ IMX_PINCTRL_PIN(GPIO1_IO08),
+ IMX_PINCTRL_PIN(GPIO1_IO09),
+ IMX_PINCTRL_PIN(GPIO1_IO10),
+ IMX_PINCTRL_PIN(GPIO1_IO11),
+ IMX_PINCTRL_PIN(GPIO1_IO12),
+ IMX_PINCTRL_PIN(GPIO1_IO13),
+ IMX_PINCTRL_PIN(GPIO1_IO14),
+ IMX_PINCTRL_PIN(GPIO1_IO15),
+ IMX_PINCTRL_PIN(ENET_MDC),
+ IMX_PINCTRL_PIN(ENET_MDIO),
+ IMX_PINCTRL_PIN(ENET_TD3),
+ IMX_PINCTRL_PIN(ENET_TD2),
+ IMX_PINCTRL_PIN(ENET_TD1),
+ IMX_PINCTRL_PIN(ENET_TD0),
+ IMX_PINCTRL_PIN(ENET_TX_CTL),
+ IMX_PINCTRL_PIN(ENET_TXC),
+ IMX_PINCTRL_PIN(ENET_RX_CTL),
+ IMX_PINCTRL_PIN(ENET_RXC),
+ IMX_PINCTRL_PIN(ENET_RD0),
+ IMX_PINCTRL_PIN(ENET_RD1),
+ IMX_PINCTRL_PIN(ENET_RD2),
+ IMX_PINCTRL_PIN(ENET_RD3),
+ IMX_PINCTRL_PIN(SD1_CLK),
+ IMX_PINCTRL_PIN(SD1_CMD),
+ IMX_PINCTRL_PIN(SD1_DATA0),
+ IMX_PINCTRL_PIN(SD1_DATA1),
+ IMX_PINCTRL_PIN(SD1_DATA2),
+ IMX_PINCTRL_PIN(SD1_DATA3),
+ IMX_PINCTRL_PIN(SD1_DATA4),
+ IMX_PINCTRL_PIN(SD1_DATA5),
+ IMX_PINCTRL_PIN(SD1_DATA6),
+ IMX_PINCTRL_PIN(SD1_DATA7),
+ IMX_PINCTRL_PIN(SD1_RESET_B),
+ IMX_PINCTRL_PIN(SD1_STROBE),
+ IMX_PINCTRL_PIN(SD2_CD_B),
+ IMX_PINCTRL_PIN(SD2_CLK),
+ IMX_PINCTRL_PIN(SD2_CMD),
+ IMX_PINCTRL_PIN(SD2_DATA0),
+ IMX_PINCTRL_PIN(SD2_DATA1),
+ IMX_PINCTRL_PIN(SD2_DATA2),
+ IMX_PINCTRL_PIN(SD2_DATA3),
+ IMX_PINCTRL_PIN(SD2_RESET_B),
+ IMX_PINCTRL_PIN(SD2_WP),
+ IMX_PINCTRL_PIN(NAND_ALE),
+ IMX_PINCTRL_PIN(NAND_CE0),
+ IMX_PINCTRL_PIN(NAND_CE1),
+ IMX_PINCTRL_PIN(NAND_CE2),
+ IMX_PINCTRL_PIN(NAND_CE3),
+ IMX_PINCTRL_PIN(NAND_CLE),
+ IMX_PINCTRL_PIN(NAND_DATA00),
+ IMX_PINCTRL_PIN(NAND_DATA01),
+ IMX_PINCTRL_PIN(NAND_DATA02),
+ IMX_PINCTRL_PIN(NAND_DATA03),
+ IMX_PINCTRL_PIN(NAND_DATA04),
+ IMX_PINCTRL_PIN(NAND_DATA05),
+ IMX_PINCTRL_PIN(NAND_DATA06),
+ IMX_PINCTRL_PIN(NAND_DATA07),
+ IMX_PINCTRL_PIN(NAND_DQS),
+ IMX_PINCTRL_PIN(NAND_RE_B),
+ IMX_PINCTRL_PIN(NAND_READY_B),
+ IMX_PINCTRL_PIN(NAND_WE_B),
+ IMX_PINCTRL_PIN(NAND_WP_B),
+ IMX_PINCTRL_PIN(SAI5_RXFS),
+ IMX_PINCTRL_PIN(SAI5_RXC),
+ IMX_PINCTRL_PIN(SAI5_RXD0),
+ IMX_PINCTRL_PIN(SAI5_RXD1),
+ IMX_PINCTRL_PIN(SAI5_RXD2),
+ IMX_PINCTRL_PIN(SAI5_RXD3),
+ IMX_PINCTRL_PIN(SAI5_MCLK),
+ IMX_PINCTRL_PIN(SAI1_RXFS),
+ IMX_PINCTRL_PIN(SAI1_RXC),
+ IMX_PINCTRL_PIN(SAI1_RXD0),
+ IMX_PINCTRL_PIN(SAI1_RXD1),
+ IMX_PINCTRL_PIN(SAI1_RXD2),
+ IMX_PINCTRL_PIN(SAI1_RXD3),
+ IMX_PINCTRL_PIN(SAI1_RXD4),
+ IMX_PINCTRL_PIN(SAI1_RXD5),
+ IMX_PINCTRL_PIN(SAI1_RXD6),
+ IMX_PINCTRL_PIN(SAI1_RXD7),
+ IMX_PINCTRL_PIN(SAI1_TXFS),
+ IMX_PINCTRL_PIN(SAI1_TXC),
+ IMX_PINCTRL_PIN(SAI1_TXD0),
+ IMX_PINCTRL_PIN(SAI1_TXD1),
+ IMX_PINCTRL_PIN(SAI1_TXD2),
+ IMX_PINCTRL_PIN(SAI1_TXD3),
+ IMX_PINCTRL_PIN(SAI1_TXD4),
+ IMX_PINCTRL_PIN(SAI1_TXD5),
+ IMX_PINCTRL_PIN(SAI1_TXD6),
+ IMX_PINCTRL_PIN(SAI1_TXD7),
+ IMX_PINCTRL_PIN(SAI1_MCLK),
+ IMX_PINCTRL_PIN(SAI2_RXFS),
+ IMX_PINCTRL_PIN(SAI2_RXC),
+ IMX_PINCTRL_PIN(SAI2_RXD0),
+ IMX_PINCTRL_PIN(SAI2_TXFS),
+ IMX_PINCTRL_PIN(SAI2_TXC),
+ IMX_PINCTRL_PIN(SAI2_TXD0),
+ IMX_PINCTRL_PIN(SAI2_MCLK),
+ IMX_PINCTRL_PIN(SAI3_RXFS),
+ IMX_PINCTRL_PIN(SAI3_RXC),
+ IMX_PINCTRL_PIN(SAI3_RXD),
+ IMX_PINCTRL_PIN(SAI3_TXFS),
+ IMX_PINCTRL_PIN(SAI3_TXC),
+ IMX_PINCTRL_PIN(SAI3_TXD),
+ IMX_PINCTRL_PIN(SAI3_MCLK),
+ IMX_PINCTRL_PIN(SPDIF_TX),
+ IMX_PINCTRL_PIN(SPDIF_RX),
+ IMX_PINCTRL_PIN(SPDIF_EXT_CLK),
+ IMX_PINCTRL_PIN(ECSPI1_SCLK),
+ IMX_PINCTRL_PIN(ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(ECSPI1_MISO),
+ IMX_PINCTRL_PIN(ECSPI1_SS0),
+ IMX_PINCTRL_PIN(ECSPI2_SCLK),
+ IMX_PINCTRL_PIN(ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(ECSPI2_MISO),
+ IMX_PINCTRL_PIN(ECSPI2_SS0),
+ IMX_PINCTRL_PIN(I2C1_SCL),
+ IMX_PINCTRL_PIN(I2C1_SDA),
+ IMX_PINCTRL_PIN(I2C2_SCL),
+ IMX_PINCTRL_PIN(I2C2_SDA),
+ IMX_PINCTRL_PIN(I2C3_SCL),
+ IMX_PINCTRL_PIN(I2C3_SDA),
+ IMX_PINCTRL_PIN(I2C4_SCL),
+ IMX_PINCTRL_PIN(I2C4_SDA),
+ IMX_PINCTRL_PIN(UART1_RXD),
+ IMX_PINCTRL_PIN(UART1_TXD),
+ IMX_PINCTRL_PIN(UART2_RXD),
+ IMX_PINCTRL_PIN(UART2_TXD),
+ IMX_PINCTRL_PIN(UART3_RXD),
+ IMX_PINCTRL_PIN(UART3_TXD),
+ IMX_PINCTRL_PIN(UART4_RXD),
+ IMX_PINCTRL_PIN(UART4_TXD),
+};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mp.c b/drivers/pinctrl/nxp/pinctrl-imx8mp.c
new file mode 100644
index 00000000000..7f02eba5355
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx8mp.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "pinctrl-imx.h"
+
+enum imx8mp_pads {
+ RESERVE0 = 0,
+ RESERVE1 = 1,
+ RESERVE2 = 2,
+ RESERVE3 = 3,
+ RESERVE4 = 4,
+ GPIO1_IO00 = 5,
+ GPIO1_IO01 = 6,
+ GPIO1_IO02 = 7,
+ GPIO1_IO03 = 8,
+ GPIO1_IO04 = 9,
+ GPIO1_IO05 = 10,
+ GPIO1_IO06 = 11,
+ GPIO1_IO07 = 12,
+ GPIO1_IO08 = 13,
+ GPIO1_IO09 = 14,
+ GPIO1_IO10 = 15,
+ GPIO1_IO11 = 16,
+ GPIO1_IO12 = 17,
+ GPIO1_IO13 = 18,
+ GPIO1_IO14 = 19,
+ GPIO1_IO15 = 20,
+ ENET_MDC = 21,
+ ENET_MDIO = 22,
+ ENET_TD3 = 23,
+ ENET_TD2 = 24,
+ ENET_TD1 = 25,
+ ENET_TD0 = 26,
+ ENET_TX_CTL = 27,
+ ENET_TXC = 28,
+ ENET_RX_CTL = 29,
+ ENET_RXC = 30,
+ ENET_RD0 = 31,
+ ENET_RD1 = 32,
+ ENET_RD2 = 33,
+ ENET_RD3 = 34,
+ SD1_CLK = 35,
+ SD1_CMD = 36,
+ SD1_DATA0 = 37,
+ SD1_DATA1 = 38,
+ SD1_DATA2 = 39,
+ SD1_DATA3 = 40,
+ SD1_DATA4 = 41,
+ SD1_DATA5 = 42,
+ SD1_DATA6 = 43,
+ SD1_DATA7 = 44,
+ SD1_RESET_B = 45,
+ SD1_STROBE = 46,
+ SD2_CD_B = 47,
+ SD2_CLK = 48,
+ SD2_CMD = 49,
+ SD2_DATA0 = 50,
+ SD2_DATA1 = 51,
+ SD2_DATA2 = 52,
+ SD2_DATA3 = 53,
+ SD2_RESET_B = 54,
+ SD2_WP = 55,
+ NAND_ALE = 56,
+ NAND_CE0_B = 57,
+ NAND_CE1_B = 58,
+ NAND_CE2_B = 59,
+ NAND_CE3_B = 60,
+ NAND_CLE = 61,
+ NAND_DATA00 = 62,
+ NAND_DATA01 = 63,
+ NAND_DATA02 = 64,
+ NAND_DATA03 = 65,
+ NAND_DATA04 = 66,
+ NAND_DATA05 = 67,
+ NAND_DATA06 = 68,
+ NAND_DATA07 = 69,
+ NAND_DQS = 70,
+ NAND_RE_B = 71,
+ NAND_READY_B = 72,
+ NAND_WE_B = 73,
+ NAND_WP_B = 74,
+ SAI5_RXFS = 75,
+ SAI5_RXC = 76,
+ SAI5_RXD0 = 77,
+ SAI5_RXD1 = 78,
+ SAI5_RXD2 = 79,
+ SAI5_RXD3 = 80,
+ SAI5_MCLK = 81,
+ SAI1_RXFS = 82,
+ SAI1_RXC = 83,
+ SAI1_RXD0 = 84,
+ SAI1_RXD1 = 85,
+ SAI1_RXD2 = 86,
+ SAI1_RXD3 = 87,
+ SAI1_RXD4 = 88,
+ SAI1_RXD5 = 89,
+ SAI1_RXD6 = 90,
+ SAI1_RXD7 = 91,
+ SAI1_TXFS = 92,
+ SAI1_TXC = 93,
+ SAI1_TXD0 = 94,
+ SAI1_TXD1 = 95,
+ SAI1_TXD2 = 96,
+ SAI1_TXD3 = 97,
+ SAI1_TXD4 = 98,
+ SAI1_TXD5 = 99,
+ SAI1_TXD6 = 100,
+ SAI1_TXD7 = 101,
+ SAI1_MCLK = 102,
+ SAI2_RXFS = 103,
+ SAI2_RXC = 104,
+ SAI2_RXD0 = 105,
+ SAI2_TXFS = 106,
+ SAI2_TXC = 107,
+ SAI2_TXD0 = 108,
+ SAI2_MCLK = 109,
+ SAI3_RXFS = 110,
+ SAI3_RXC = 111,
+ SAI3_RXD = 112,
+ SAI3_TXFS = 113,
+ SAI3_TXC = 114,
+ SAI3_TXD = 115,
+ SAI3_MCLK = 116,
+ SPDIF_TX = 117,
+ SPDIF_RX = 118,
+ SPDIF_EXT_CLK = 119,
+ ECSPI1_SCLK = 120,
+ ECSPI1_MOSI = 121,
+ ECSPI1_MISO = 122,
+ ECSPI1_SS0 = 123,
+ ECSPI2_SCLK = 124,
+ ECSPI2_MOSI = 125,
+ ECSPI2_MISO = 126,
+ ECSPI2_SS0 = 127,
+ I2C1_SCL = 128,
+ I2C1_SDA = 129,
+ I2C2_SCL = 130,
+ I2C2_SDA = 131,
+ I2C3_SCL = 132,
+ I2C3_SDA = 133,
+ I2C4_SCL = 134,
+ I2C4_SDA = 135,
+ UART1_RXD = 136,
+ UART1_TXD = 137,
+ UART2_RXD = 138,
+ UART2_TXD = 139,
+ UART3_RXD = 140,
+ UART3_TXD = 141,
+ UART4_RXD = 142,
+ UART4_TXD = 143,
+ HDMI_DDC_SCL = 144,
+ HDMI_DDC_SDA = 145,
+ HDMI_CEC = 146,
+ HDMI_HPD = 147,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(RESERVE0),
+ IMX_PINCTRL_PIN(RESERVE1),
+ IMX_PINCTRL_PIN(RESERVE2),
+ IMX_PINCTRL_PIN(RESERVE3),
+ IMX_PINCTRL_PIN(RESERVE4),
+ IMX_PINCTRL_PIN(GPIO1_IO00),
+ IMX_PINCTRL_PIN(GPIO1_IO01),
+ IMX_PINCTRL_PIN(GPIO1_IO02),
+ IMX_PINCTRL_PIN(GPIO1_IO03),
+ IMX_PINCTRL_PIN(GPIO1_IO04),
+ IMX_PINCTRL_PIN(GPIO1_IO05),
+ IMX_PINCTRL_PIN(GPIO1_IO06),
+ IMX_PINCTRL_PIN(GPIO1_IO07),
+ IMX_PINCTRL_PIN(GPIO1_IO08),
+ IMX_PINCTRL_PIN(GPIO1_IO09),
+ IMX_PINCTRL_PIN(GPIO1_IO10),
+ IMX_PINCTRL_PIN(GPIO1_IO11),
+ IMX_PINCTRL_PIN(GPIO1_IO12),
+ IMX_PINCTRL_PIN(GPIO1_IO13),
+ IMX_PINCTRL_PIN(GPIO1_IO14),
+ IMX_PINCTRL_PIN(GPIO1_IO15),
+ IMX_PINCTRL_PIN(ENET_MDC),
+ IMX_PINCTRL_PIN(ENET_MDIO),
+ IMX_PINCTRL_PIN(ENET_TD3),
+ IMX_PINCTRL_PIN(ENET_TD2),
+ IMX_PINCTRL_PIN(ENET_TD1),
+ IMX_PINCTRL_PIN(ENET_TD0),
+ IMX_PINCTRL_PIN(ENET_TX_CTL),
+ IMX_PINCTRL_PIN(ENET_TXC),
+ IMX_PINCTRL_PIN(ENET_RX_CTL),
+ IMX_PINCTRL_PIN(ENET_RXC),
+ IMX_PINCTRL_PIN(ENET_RD0),
+ IMX_PINCTRL_PIN(ENET_RD1),
+ IMX_PINCTRL_PIN(ENET_RD2),
+ IMX_PINCTRL_PIN(ENET_RD3),
+ IMX_PINCTRL_PIN(SD1_CLK),
+ IMX_PINCTRL_PIN(SD1_CMD),
+ IMX_PINCTRL_PIN(SD1_DATA0),
+ IMX_PINCTRL_PIN(SD1_DATA1),
+ IMX_PINCTRL_PIN(SD1_DATA2),
+ IMX_PINCTRL_PIN(SD1_DATA3),
+ IMX_PINCTRL_PIN(SD1_DATA4),
+ IMX_PINCTRL_PIN(SD1_DATA5),
+ IMX_PINCTRL_PIN(SD1_DATA6),
+ IMX_PINCTRL_PIN(SD1_DATA7),
+ IMX_PINCTRL_PIN(SD1_RESET_B),
+ IMX_PINCTRL_PIN(SD1_STROBE),
+ IMX_PINCTRL_PIN(SD2_CD_B),
+ IMX_PINCTRL_PIN(SD2_CLK),
+ IMX_PINCTRL_PIN(SD2_CMD),
+ IMX_PINCTRL_PIN(SD2_DATA0),
+ IMX_PINCTRL_PIN(SD2_DATA1),
+ IMX_PINCTRL_PIN(SD2_DATA2),
+ IMX_PINCTRL_PIN(SD2_DATA3),
+ IMX_PINCTRL_PIN(SD2_RESET_B),
+ IMX_PINCTRL_PIN(SD2_WP),
+ IMX_PINCTRL_PIN(NAND_ALE),
+ IMX_PINCTRL_PIN(NAND_CE0_B),
+ IMX_PINCTRL_PIN(NAND_CE1_B),
+ IMX_PINCTRL_PIN(NAND_CE2_B),
+ IMX_PINCTRL_PIN(NAND_CE3_B),
+ IMX_PINCTRL_PIN(NAND_CLE),
+ IMX_PINCTRL_PIN(NAND_DATA00),
+ IMX_PINCTRL_PIN(NAND_DATA01),
+ IMX_PINCTRL_PIN(NAND_DATA02),
+ IMX_PINCTRL_PIN(NAND_DATA03),
+ IMX_PINCTRL_PIN(NAND_DATA04),
+ IMX_PINCTRL_PIN(NAND_DATA05),
+ IMX_PINCTRL_PIN(NAND_DATA06),
+ IMX_PINCTRL_PIN(NAND_DATA07),
+ IMX_PINCTRL_PIN(NAND_DQS),
+ IMX_PINCTRL_PIN(NAND_RE_B),
+ IMX_PINCTRL_PIN(NAND_READY_B),
+ IMX_PINCTRL_PIN(NAND_WE_B),
+ IMX_PINCTRL_PIN(NAND_WP_B),
+ IMX_PINCTRL_PIN(SAI5_RXFS),
+ IMX_PINCTRL_PIN(SAI5_RXC),
+ IMX_PINCTRL_PIN(SAI5_RXD0),
+ IMX_PINCTRL_PIN(SAI5_RXD1),
+ IMX_PINCTRL_PIN(SAI5_RXD2),
+ IMX_PINCTRL_PIN(SAI5_RXD3),
+ IMX_PINCTRL_PIN(SAI5_MCLK),
+ IMX_PINCTRL_PIN(SAI1_RXFS),
+ IMX_PINCTRL_PIN(SAI1_RXC),
+ IMX_PINCTRL_PIN(SAI1_RXD0),
+ IMX_PINCTRL_PIN(SAI1_RXD1),
+ IMX_PINCTRL_PIN(SAI1_RXD2),
+ IMX_PINCTRL_PIN(SAI1_RXD3),
+ IMX_PINCTRL_PIN(SAI1_RXD4),
+ IMX_PINCTRL_PIN(SAI1_RXD5),
+ IMX_PINCTRL_PIN(SAI1_RXD6),
+ IMX_PINCTRL_PIN(SAI1_RXD7),
+ IMX_PINCTRL_PIN(SAI1_TXFS),
+ IMX_PINCTRL_PIN(SAI1_TXC),
+ IMX_PINCTRL_PIN(SAI1_TXD0),
+ IMX_PINCTRL_PIN(SAI1_TXD1),
+ IMX_PINCTRL_PIN(SAI1_TXD2),
+ IMX_PINCTRL_PIN(SAI1_TXD3),
+ IMX_PINCTRL_PIN(SAI1_TXD4),
+ IMX_PINCTRL_PIN(SAI1_TXD5),
+ IMX_PINCTRL_PIN(SAI1_TXD6),
+ IMX_PINCTRL_PIN(SAI1_TXD7),
+ IMX_PINCTRL_PIN(SAI1_MCLK),
+ IMX_PINCTRL_PIN(SAI2_RXFS),
+ IMX_PINCTRL_PIN(SAI2_RXC),
+ IMX_PINCTRL_PIN(SAI2_RXD0),
+ IMX_PINCTRL_PIN(SAI2_TXFS),
+ IMX_PINCTRL_PIN(SAI2_TXC),
+ IMX_PINCTRL_PIN(SAI2_TXD0),
+ IMX_PINCTRL_PIN(SAI2_MCLK),
+ IMX_PINCTRL_PIN(SAI3_RXFS),
+ IMX_PINCTRL_PIN(SAI3_RXC),
+ IMX_PINCTRL_PIN(SAI3_RXD),
+ IMX_PINCTRL_PIN(SAI3_TXFS),
+ IMX_PINCTRL_PIN(SAI3_TXC),
+ IMX_PINCTRL_PIN(SAI3_TXD),
+ IMX_PINCTRL_PIN(SAI3_MCLK),
+ IMX_PINCTRL_PIN(SPDIF_TX),
+ IMX_PINCTRL_PIN(SPDIF_RX),
+ IMX_PINCTRL_PIN(SPDIF_EXT_CLK),
+ IMX_PINCTRL_PIN(ECSPI1_SCLK),
+ IMX_PINCTRL_PIN(ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(ECSPI1_MISO),
+ IMX_PINCTRL_PIN(ECSPI1_SS0),
+ IMX_PINCTRL_PIN(ECSPI2_SCLK),
+ IMX_PINCTRL_PIN(ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(ECSPI2_MISO),
+ IMX_PINCTRL_PIN(ECSPI2_SS0),
+ IMX_PINCTRL_PIN(I2C1_SCL),
+ IMX_PINCTRL_PIN(I2C1_SDA),
+ IMX_PINCTRL_PIN(I2C2_SCL),
+ IMX_PINCTRL_PIN(I2C2_SDA),
+ IMX_PINCTRL_PIN(I2C3_SCL),
+ IMX_PINCTRL_PIN(I2C3_SDA),
+ IMX_PINCTRL_PIN(I2C4_SCL),
+ IMX_PINCTRL_PIN(I2C4_SDA),
+ IMX_PINCTRL_PIN(UART1_RXD),
+ IMX_PINCTRL_PIN(UART1_TXD),
+ IMX_PINCTRL_PIN(UART2_RXD),
+ IMX_PINCTRL_PIN(UART2_TXD),
+ IMX_PINCTRL_PIN(UART3_RXD),
+ IMX_PINCTRL_PIN(UART3_TXD),
+ IMX_PINCTRL_PIN(UART4_RXD),
+ IMX_PINCTRL_PIN(UART4_TXD),
+ IMX_PINCTRL_PIN(HDMI_DDC_SCL),
+ IMX_PINCTRL_PIN(HDMI_DDC_SDA),
+ IMX_PINCTRL_PIN(HDMI_CEC),
+ IMX_PINCTRL_PIN(HDMI_HPD),
+};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mq.c b/drivers/pinctrl/nxp/pinctrl-imx8mq.c
new file mode 100644
index 00000000000..bcc3e8ecbcf
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx8mq.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "pinctrl-imx.h"
+
+enum imx8mq_pads {
+ RESERVE0 = 0,
+ RESERVE1 = 1,
+ RESERVE2 = 2,
+ RESERVE3 = 3,
+ RESERVE4 = 4,
+ PMIC_STBY_REQ_CCMSRCGPCMIX = 5,
+ PMIC_ON_REQ_SNVSMIX = 6,
+ ONOFF_SNVSMIX = 7,
+ POR_B_SNVSMIX = 8,
+ RTC_RESET_B_SNVSMIX = 9,
+ GPIO1_IO00 = 10,
+ GPIO1_IO01 = 11,
+ GPIO1_IO02 = 12,
+ GPIO1_IO03 = 13,
+ GPIO1_IO04 = 14,
+ GPIO1_IO05 = 15,
+ GPIO1_IO06 = 16,
+ GPIO1_IO07 = 17,
+ GPIO1_IO08 = 18,
+ GPIO1_IO09 = 19,
+ GPIO1_IO10 = 20,
+ GPIO1_IO11 = 21,
+ GPIO1_IO12 = 22,
+ GPIO1_IO13 = 23,
+ GPIO1_IO14 = 24,
+ GPIO1_IO15 = 25,
+ ENET_MDC = 26,
+ ENET_MDIO = 27,
+ ENET_TD3 = 28,
+ ENET_TD2 = 29,
+ ENET_TD1 = 30,
+ ENET_TD0 = 31,
+ ENET_TX_CTL = 32,
+ ENET_TXC = 33,
+ ENET_RX_CTL = 34,
+ ENET_RXC = 35,
+ ENET_RD0 = 36,
+ ENET_RD1 = 37,
+ ENET_RD2 = 38,
+ ENET_RD3 = 39,
+ SD1_CLK = 40,
+ SD1_CMD = 41,
+ SD1_DATA0 = 42,
+ SD1_DATA1 = 43,
+ SD1_DATA2 = 44,
+ SD1_DATA3 = 45,
+ SD1_DATA4 = 46,
+ SD1_DATA5 = 47,
+ SD1_DATA6 = 48,
+ SD1_DATA7 = 49,
+ SD1_RESET_B = 50,
+ SD1_STROBE = 51,
+ SD2_CD_B = 52,
+ SD2_CLK = 53,
+ SD2_CMD = 54,
+ SD2_DATA0 = 55,
+ SD2_DATA1 = 56,
+ SD2_DATA2 = 57,
+ SD2_DATA3 = 58,
+ SD2_RESET_B = 59,
+ SD2_WP = 60,
+ NAND_ALE = 61,
+ NAND_CE0_B = 62,
+ NAND_CE1_B = 63,
+ NAND_CE2_B = 64,
+ NAND_CE3_B = 65,
+ NAND_CLE = 66,
+ NAND_DATA00 = 67,
+ NAND_DATA01 = 68,
+ NAND_DATA02 = 69,
+ NAND_DATA03 = 70,
+ NAND_DATA04 = 71,
+ NAND_DATA05 = 72,
+ NAND_DATA06 = 73,
+ NAND_DATA07 = 74,
+ NAND_DQS = 75,
+ NAND_RE_B = 76,
+ NAND_READY_B = 77,
+ NAND_WE_B = 78,
+ NAND_WP_B = 79,
+ SAI5_RXFS = 80,
+ SAI5_RXC = 81,
+ SAI5_RXD0 = 82,
+ SAI5_RXD1 = 83,
+ SAI5_RXD2 = 84,
+ SAI5_RXD3 = 85,
+ SAI5_MCLK = 86,
+ SAI1_RXFS = 87,
+ SAI1_RXC = 88,
+ SAI1_RXD0 = 89,
+ SAI1_RXD1 = 90,
+ SAI1_RXD2 = 91,
+ SAI1_RXD3 = 92,
+ SAI1_RXD4 = 93,
+ SAI1_RXD5 = 94,
+ SAI1_RXD6 = 95,
+ SAI1_RXD7 = 96,
+ SAI1_TXFS = 97,
+ SAI1_TXC = 98,
+ SAI1_TXD0 = 99,
+ SAI1_TXD1 = 100,
+ SAI1_TXD2 = 101,
+ SAI1_TXD3 = 102,
+ SAI1_TXD4 = 103,
+ SAI1_TXD5 = 104,
+ SAI1_TXD6 = 105,
+ SAI1_TXD7 = 106,
+ SAI1_MCLK = 107,
+ SAI2_RXFS = 108,
+ SAI2_RXC = 109,
+ SAI2_RXD0 = 110,
+ SAI2_TXFS = 111,
+ SAI2_TXC = 112,
+ SAI2_TXD0 = 113,
+ SAI2_MCLK = 114,
+ SAI3_RXFS = 115,
+ SAI3_RXC = 116,
+ SAI3_RXD = 117,
+ SAI3_TXFS = 118,
+ SAI3_TXC = 119,
+ SAI3_TXD = 120,
+ SAI3_MCLK = 121,
+ SPDIF_TX = 122,
+ SPDIF_RX = 123,
+ SPDIF_EXT_CLK = 124,
+ ECSPI1_SCLK = 125,
+ ECSPI1_MOSI = 126,
+ ECSPI1_MISO = 127,
+ ECSPI1_SS0 = 128,
+ ECSPI2_SCLK = 129,
+ ECSPI2_MOSI = 130,
+ ECSPI2_MISO = 131,
+ ECSPI2_SS0 = 132,
+ I2C1_SCL = 133,
+ I2C1_SDA = 134,
+ I2C2_SCL = 135,
+ I2C2_SDA = 136,
+ I2C3_SCL = 137,
+ I2C3_SDA = 138,
+ I2C4_SCL = 139,
+ I2C4_SDA = 140,
+ UART1_RXD = 141,
+ UART1_TXD = 142,
+ UART2_RXD = 143,
+ UART2_TXD = 144,
+ UART3_RXD = 145,
+ UART3_TXD = 146,
+ UART4_RXD = 147,
+ UART4_TXD = 148,
+};
+
+static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(RESERVE0),
+ IMX_PINCTRL_PIN(RESERVE1),
+ IMX_PINCTRL_PIN(RESERVE2),
+ IMX_PINCTRL_PIN(RESERVE3),
+ IMX_PINCTRL_PIN(RESERVE4),
+ IMX_PINCTRL_PIN(PMIC_STBY_REQ_CCMSRCGPCMIX),
+ IMX_PINCTRL_PIN(PMIC_ON_REQ_SNVSMIX),
+ IMX_PINCTRL_PIN(ONOFF_SNVSMIX),
+ IMX_PINCTRL_PIN(POR_B_SNVSMIX),
+ IMX_PINCTRL_PIN(RTC_RESET_B_SNVSMIX),
+ IMX_PINCTRL_PIN(GPIO1_IO00),
+ IMX_PINCTRL_PIN(GPIO1_IO01),
+ IMX_PINCTRL_PIN(GPIO1_IO02),
+ IMX_PINCTRL_PIN(GPIO1_IO03),
+ IMX_PINCTRL_PIN(GPIO1_IO04),
+ IMX_PINCTRL_PIN(GPIO1_IO05),
+ IMX_PINCTRL_PIN(GPIO1_IO06),
+ IMX_PINCTRL_PIN(GPIO1_IO07),
+ IMX_PINCTRL_PIN(GPIO1_IO08),
+ IMX_PINCTRL_PIN(GPIO1_IO09),
+ IMX_PINCTRL_PIN(GPIO1_IO10),
+ IMX_PINCTRL_PIN(GPIO1_IO11),
+ IMX_PINCTRL_PIN(GPIO1_IO12),
+ IMX_PINCTRL_PIN(GPIO1_IO13),
+ IMX_PINCTRL_PIN(GPIO1_IO14),
+ IMX_PINCTRL_PIN(GPIO1_IO15),
+ IMX_PINCTRL_PIN(ENET_MDC),
+ IMX_PINCTRL_PIN(ENET_MDIO),
+ IMX_PINCTRL_PIN(ENET_TD3),
+ IMX_PINCTRL_PIN(ENET_TD2),
+ IMX_PINCTRL_PIN(ENET_TD1),
+ IMX_PINCTRL_PIN(ENET_TD0),
+ IMX_PINCTRL_PIN(ENET_TX_CTL),
+ IMX_PINCTRL_PIN(ENET_TXC),
+ IMX_PINCTRL_PIN(ENET_RX_CTL),
+ IMX_PINCTRL_PIN(ENET_RXC),
+ IMX_PINCTRL_PIN(ENET_RD0),
+ IMX_PINCTRL_PIN(ENET_RD1),
+ IMX_PINCTRL_PIN(ENET_RD2),
+ IMX_PINCTRL_PIN(ENET_RD3),
+ IMX_PINCTRL_PIN(SD1_CLK),
+ IMX_PINCTRL_PIN(SD1_CMD),
+ IMX_PINCTRL_PIN(SD1_DATA0),
+ IMX_PINCTRL_PIN(SD1_DATA1),
+ IMX_PINCTRL_PIN(SD1_DATA2),
+ IMX_PINCTRL_PIN(SD1_DATA3),
+ IMX_PINCTRL_PIN(SD1_DATA4),
+ IMX_PINCTRL_PIN(SD1_DATA5),
+ IMX_PINCTRL_PIN(SD1_DATA6),
+ IMX_PINCTRL_PIN(SD1_DATA7),
+ IMX_PINCTRL_PIN(SD1_RESET_B),
+ IMX_PINCTRL_PIN(SD1_STROBE),
+ IMX_PINCTRL_PIN(SD2_CD_B),
+ IMX_PINCTRL_PIN(SD2_CLK),
+ IMX_PINCTRL_PIN(SD2_CMD),
+ IMX_PINCTRL_PIN(SD2_DATA0),
+ IMX_PINCTRL_PIN(SD2_DATA1),
+ IMX_PINCTRL_PIN(SD2_DATA2),
+ IMX_PINCTRL_PIN(SD2_DATA3),
+ IMX_PINCTRL_PIN(SD2_RESET_B),
+ IMX_PINCTRL_PIN(SD2_WP),
+ IMX_PINCTRL_PIN(NAND_ALE),
+ IMX_PINCTRL_PIN(NAND_CE0_B),
+ IMX_PINCTRL_PIN(NAND_CE1_B),
+ IMX_PINCTRL_PIN(NAND_CE2_B),
+ IMX_PINCTRL_PIN(NAND_CE3_B),
+ IMX_PINCTRL_PIN(NAND_CLE),
+ IMX_PINCTRL_PIN(NAND_DATA00),
+ IMX_PINCTRL_PIN(NAND_DATA01),
+ IMX_PINCTRL_PIN(NAND_DATA02),
+ IMX_PINCTRL_PIN(NAND_DATA03),
+ IMX_PINCTRL_PIN(NAND_DATA04),
+ IMX_PINCTRL_PIN(NAND_DATA05),
+ IMX_PINCTRL_PIN(NAND_DATA06),
+ IMX_PINCTRL_PIN(NAND_DATA07),
+ IMX_PINCTRL_PIN(NAND_DQS),
+ IMX_PINCTRL_PIN(NAND_RE_B),
+ IMX_PINCTRL_PIN(NAND_READY_B),
+ IMX_PINCTRL_PIN(NAND_WE_B),
+ IMX_PINCTRL_PIN(NAND_WP_B),
+ IMX_PINCTRL_PIN(SAI5_RXFS),
+ IMX_PINCTRL_PIN(SAI5_RXC),
+ IMX_PINCTRL_PIN(SAI5_RXD0),
+ IMX_PINCTRL_PIN(SAI5_RXD1),
+ IMX_PINCTRL_PIN(SAI5_RXD2),
+ IMX_PINCTRL_PIN(SAI5_RXD3),
+ IMX_PINCTRL_PIN(SAI5_MCLK),
+ IMX_PINCTRL_PIN(SAI1_RXFS),
+ IMX_PINCTRL_PIN(SAI1_RXC),
+ IMX_PINCTRL_PIN(SAI1_RXD0),
+ IMX_PINCTRL_PIN(SAI1_RXD1),
+ IMX_PINCTRL_PIN(SAI1_RXD2),
+ IMX_PINCTRL_PIN(SAI1_RXD3),
+ IMX_PINCTRL_PIN(SAI1_RXD4),
+ IMX_PINCTRL_PIN(SAI1_RXD5),
+ IMX_PINCTRL_PIN(SAI1_RXD6),
+ IMX_PINCTRL_PIN(SAI1_RXD7),
+ IMX_PINCTRL_PIN(SAI1_TXFS),
+ IMX_PINCTRL_PIN(SAI1_TXC),
+ IMX_PINCTRL_PIN(SAI1_TXD0),
+ IMX_PINCTRL_PIN(SAI1_TXD1),
+ IMX_PINCTRL_PIN(SAI1_TXD2),
+ IMX_PINCTRL_PIN(SAI1_TXD3),
+ IMX_PINCTRL_PIN(SAI1_TXD4),
+ IMX_PINCTRL_PIN(SAI1_TXD5),
+ IMX_PINCTRL_PIN(SAI1_TXD6),
+ IMX_PINCTRL_PIN(SAI1_TXD7),
+ IMX_PINCTRL_PIN(SAI1_MCLK),
+ IMX_PINCTRL_PIN(SAI2_RXFS),
+ IMX_PINCTRL_PIN(SAI2_RXC),
+ IMX_PINCTRL_PIN(SAI2_RXD0),
+ IMX_PINCTRL_PIN(SAI2_TXFS),
+ IMX_PINCTRL_PIN(SAI2_TXC),
+ IMX_PINCTRL_PIN(SAI2_TXD0),
+ IMX_PINCTRL_PIN(SAI2_MCLK),
+ IMX_PINCTRL_PIN(SAI3_RXFS),
+ IMX_PINCTRL_PIN(SAI3_RXC),
+ IMX_PINCTRL_PIN(SAI3_RXD),
+ IMX_PINCTRL_PIN(SAI3_TXFS),
+ IMX_PINCTRL_PIN(SAI3_TXC),
+ IMX_PINCTRL_PIN(SAI3_TXD),
+ IMX_PINCTRL_PIN(SAI3_MCLK),
+ IMX_PINCTRL_PIN(SPDIF_TX),
+ IMX_PINCTRL_PIN(SPDIF_RX),
+ IMX_PINCTRL_PIN(SPDIF_EXT_CLK),
+ IMX_PINCTRL_PIN(ECSPI1_SCLK),
+ IMX_PINCTRL_PIN(ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(ECSPI1_MISO),
+ IMX_PINCTRL_PIN(ECSPI1_SS0),
+ IMX_PINCTRL_PIN(ECSPI2_SCLK),
+ IMX_PINCTRL_PIN(ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(ECSPI2_MISO),
+ IMX_PINCTRL_PIN(ECSPI2_SS0),
+ IMX_PINCTRL_PIN(I2C1_SCL),
+ IMX_PINCTRL_PIN(I2C1_SDA),
+ IMX_PINCTRL_PIN(I2C2_SCL),
+ IMX_PINCTRL_PIN(I2C2_SDA),
+ IMX_PINCTRL_PIN(I2C3_SCL),
+ IMX_PINCTRL_PIN(I2C3_SDA),
+ IMX_PINCTRL_PIN(I2C4_SCL),
+ IMX_PINCTRL_PIN(I2C4_SDA),
+ IMX_PINCTRL_PIN(UART1_RXD),
+ IMX_PINCTRL_PIN(UART1_TXD),
+ IMX_PINCTRL_PIN(UART2_RXD),
+ IMX_PINCTRL_PIN(UART2_TXD),
+ IMX_PINCTRL_PIN(UART3_RXD),
+ IMX_PINCTRL_PIN(UART3_TXD),
+ IMX_PINCTRL_PIN(UART4_RXD),
+ IMX_PINCTRL_PIN(UART4_TXD),
+};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx9.c b/drivers/pinctrl/nxp/pinctrl-imx9.c
new file mode 100644
index 00000000000..de22e29e953
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx9.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <asm/io.h>
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imx9_pinctrl_soc_info __section(".data") = {
+ .flags = ZERO_OFFSET_VALID,
+};
+
+static const struct udevice_id imx9_pinctrl_match[] = {
+#if IS_ENABLED(CONFIG_IMX93)
+ { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx9_pinctrl_soc_info },
+#endif
+#if IS_ENABLED(CONFIG_IMX91)
+ { .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx9_pinctrl_soc_info },
+#endif
+ { /* sentinel */ }
+};
+
+#if CONFIG_IS_ENABLED(CMD_PINMUX)
+
+#if IS_ENABLED(CONFIG_IMX93)
+#include "pinctrl-imx93.c"
+#elif IS_ENABLED(CONFIG_IMX91)
+#include "pinctrl-imx91.c"
+#endif
+
+static int imx9_get_pins_count(struct udevice *dev)
+{
+ return ARRAY_SIZE(imx9_pinctrl_pads);
+}
+
+static const char *imx9_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+ /* sanity checking */
+ if (selector != imx9_pinctrl_pads[selector].number) {
+ dev_err(dev,
+ "selector(%u) not match with imx9_pinctrl_pads[selector].number(%u)\n",
+ selector, imx9_pinctrl_pads[selector].number);
+ return NULL;
+ }
+
+ return imx9_pinctrl_pads[selector].name;
+}
+
+static int imx9_get_pin_muxing(struct udevice *dev, unsigned int selector,
+ char *buf, int size)
+{
+ struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+ struct imx_pinctrl_soc_info *info = priv->info;
+ u32 mux_reg = selector << 2;
+ u32 mux_mode = readl(info->base + mux_reg);
+ u32 sion = mux_mode >> 4;
+
+ snprintf(buf, size, "Function(%d) SION(%d) at: 0x%p", mux_mode & 0x7, sion,
+ info->base + mux_reg);
+
+ return 0;
+}
+#endif
+
+static const struct pinctrl_ops imx9_pinctrl_ops = {
+#if CONFIG_IS_ENABLED(CMD_PINMUX)
+ .get_pin_name = imx9_get_pin_name,
+ .get_pins_count = imx9_get_pins_count,
+ .get_pin_muxing = imx9_get_pin_muxing,
+#endif
+ .set_state = imx_pinctrl_set_state_mmio,
+};
+
+U_BOOT_DRIVER(imx9_pinctrl) = {
+ .name = "imx9-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imx9_pinctrl_match),
+ .probe = imx_pinctrl_probe_mmio,
+ .remove = imx_pinctrl_remove_mmio,
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
+ .ops = &imx9_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx91.c b/drivers/pinctrl/nxp/pinctrl-imx91.c
new file mode 100644
index 00000000000..1dc63cda2fd
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx91.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "pinctrl-imx.h"
+
+enum imx91_pads {
+ DAP_TDI = 0,
+ DAP_TMS_SWDIO = 1,
+ DAP_TCLK_SWCLK = 2,
+ DAP_TDO_TRACESWO = 3,
+ GPIO_IO00 = 4,
+ GPIO_IO01 = 5,
+ GPIO_IO02 = 6,
+ GPIO_IO03 = 7,
+ GPIO_IO04 = 8,
+ GPIO_IO05 = 9,
+ GPIO_IO06 = 10,
+ GPIO_IO07 = 11,
+ GPIO_IO08 = 12,
+ GPIO_IO09 = 13,
+ GPIO_IO10 = 14,
+ GPIO_IO11 = 15,
+ GPIO_IO12 = 16,
+ GPIO_IO13 = 17,
+ GPIO_IO14 = 18,
+ GPIO_IO15 = 19,
+ GPIO_IO16 = 20,
+ GPIO_IO17 = 21,
+ GPIO_IO18 = 22,
+ GPIO_IO19 = 23,
+ GPIO_IO20 = 24,
+ GPIO_IO21 = 25,
+ GPIO_IO22 = 26,
+ GPIO_IO23 = 27,
+ GPIO_IO24 = 28,
+ GPIO_IO25 = 29,
+ GPIO_IO26 = 30,
+ GPIO_IO27 = 31,
+ GPIO_IO28 = 32,
+ GPIO_IO29 = 33,
+ CCM_CLKO1 = 34,
+ CCM_CLKO2 = 35,
+ CCM_CLKO3 = 36,
+ CCM_CLKO4 = 37,
+ ENET1_MDC = 38,
+ ENET1_MDIO = 39,
+ ENET1_TD3 = 40,
+ ENET1_TD2 = 41,
+ ENET1_TD1 = 42,
+ ENET1_TD0 = 43,
+ ENET1_TX_CTL = 44,
+ ENET1_TXC = 45,
+ ENET1_RX_CTL = 46,
+ ENET1_RXC = 47,
+ ENET1_RD0 = 48,
+ ENET1_RD1 = 49,
+ ENET1_RD2 = 50,
+ ENET1_RD3 = 51,
+ ENET2_MDC = 52,
+ ENET2_MDIO = 53,
+ ENET2_TD3 = 54,
+ ENET2_TD2 = 55,
+ ENET2_TD1 = 56,
+ ENET2_TD0 = 57,
+ ENET2_TX_CTL = 58,
+ ENET2_TXC = 59,
+ ENET2_RX_CTL = 60,
+ ENET2_RXC = 61,
+ ENET2_RD0 = 62,
+ ENET2_RD1 = 63,
+ ENET2_RD2 = 64,
+ ENET2_RD3 = 65,
+ SD1_CLK = 66,
+ SD1_CMD = 67,
+ SD1_DATA0 = 68,
+ SD1_DATA1 = 69,
+ SD1_DATA2 = 70,
+ SD1_DATA3 = 71,
+ SD1_DATA4 = 72,
+ SD1_DATA5 = 73,
+ SD1_DATA6 = 74,
+ SD1_DATA7 = 75,
+ SD1_STROBE = 76,
+ SD2_VSELECT = 77,
+ SD3_CLK = 78,
+ SD3_CMD = 79,
+ SD3_DATA0 = 80,
+ SD3_DATA1 = 81,
+ SD3_DATA2 = 82,
+ SD3_DATA3 = 83,
+ SD2_CD_B = 84,
+ SD2_CLK = 85,
+ SD2_CMD = 86,
+ SD2_DATA0 = 87,
+ SD2_DATA1 = 88,
+ SD2_DATA2 = 89,
+ SD2_DATA3 = 90,
+ SD2_RESET_B = 91,
+ I2C1_SCL = 92,
+ I2C1_SDA = 93,
+ I2C2_SCL = 94,
+ I2C2_SDA = 95,
+ UART1_RXD = 96,
+ UART1_TXD = 97,
+ UART2_RXD = 98,
+ UART2_TXD = 99,
+ PDM_CLK = 100,
+ PDM_BIT_STREAM0 = 101,
+ PDM_BIT_STREAM1 = 102,
+ SAI1_TXFS = 103,
+ SAI1_TXC = 104,
+ SAI1_TXD0 = 105,
+ SAI1_RXD0 = 106,
+ WDOG_ANY = 107,
+};
+
+static const struct imx_pinctrl_pin_desc imx9_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(DAP_TDI),
+ IMX_PINCTRL_PIN(DAP_TMS_SWDIO),
+ IMX_PINCTRL_PIN(DAP_TCLK_SWCLK),
+ IMX_PINCTRL_PIN(DAP_TDO_TRACESWO),
+ IMX_PINCTRL_PIN(GPIO_IO00),
+ IMX_PINCTRL_PIN(GPIO_IO01),
+ IMX_PINCTRL_PIN(GPIO_IO02),
+ IMX_PINCTRL_PIN(GPIO_IO03),
+ IMX_PINCTRL_PIN(GPIO_IO04),
+ IMX_PINCTRL_PIN(GPIO_IO05),
+ IMX_PINCTRL_PIN(GPIO_IO06),
+ IMX_PINCTRL_PIN(GPIO_IO07),
+ IMX_PINCTRL_PIN(GPIO_IO08),
+ IMX_PINCTRL_PIN(GPIO_IO09),
+ IMX_PINCTRL_PIN(GPIO_IO10),
+ IMX_PINCTRL_PIN(GPIO_IO11),
+ IMX_PINCTRL_PIN(GPIO_IO12),
+ IMX_PINCTRL_PIN(GPIO_IO13),
+ IMX_PINCTRL_PIN(GPIO_IO14),
+ IMX_PINCTRL_PIN(GPIO_IO15),
+ IMX_PINCTRL_PIN(GPIO_IO16),
+ IMX_PINCTRL_PIN(GPIO_IO17),
+ IMX_PINCTRL_PIN(GPIO_IO18),
+ IMX_PINCTRL_PIN(GPIO_IO19),
+ IMX_PINCTRL_PIN(GPIO_IO20),
+ IMX_PINCTRL_PIN(GPIO_IO21),
+ IMX_PINCTRL_PIN(GPIO_IO22),
+ IMX_PINCTRL_PIN(GPIO_IO23),
+ IMX_PINCTRL_PIN(GPIO_IO24),
+ IMX_PINCTRL_PIN(GPIO_IO25),
+ IMX_PINCTRL_PIN(GPIO_IO26),
+ IMX_PINCTRL_PIN(GPIO_IO27),
+ IMX_PINCTRL_PIN(GPIO_IO28),
+ IMX_PINCTRL_PIN(GPIO_IO29),
+ IMX_PINCTRL_PIN(CCM_CLKO1),
+ IMX_PINCTRL_PIN(CCM_CLKO2),
+ IMX_PINCTRL_PIN(CCM_CLKO3),
+ IMX_PINCTRL_PIN(CCM_CLKO4),
+ IMX_PINCTRL_PIN(ENET1_MDC),
+ IMX_PINCTRL_PIN(ENET1_MDIO),
+ IMX_PINCTRL_PIN(ENET1_TD3),
+ IMX_PINCTRL_PIN(ENET1_TD2),
+ IMX_PINCTRL_PIN(ENET1_TD1),
+ IMX_PINCTRL_PIN(ENET1_TD0),
+ IMX_PINCTRL_PIN(ENET1_TX_CTL),
+ IMX_PINCTRL_PIN(ENET1_TXC),
+ IMX_PINCTRL_PIN(ENET1_RX_CTL),
+ IMX_PINCTRL_PIN(ENET1_RXC),
+ IMX_PINCTRL_PIN(ENET1_RD0),
+ IMX_PINCTRL_PIN(ENET1_RD1),
+ IMX_PINCTRL_PIN(ENET1_RD2),
+ IMX_PINCTRL_PIN(ENET1_RD3),
+ IMX_PINCTRL_PIN(ENET2_MDC),
+ IMX_PINCTRL_PIN(ENET2_MDIO),
+ IMX_PINCTRL_PIN(ENET2_TD3),
+ IMX_PINCTRL_PIN(ENET2_TD2),
+ IMX_PINCTRL_PIN(ENET2_TD1),
+ IMX_PINCTRL_PIN(ENET2_TD0),
+ IMX_PINCTRL_PIN(ENET2_TX_CTL),
+ IMX_PINCTRL_PIN(ENET2_TXC),
+ IMX_PINCTRL_PIN(ENET2_RX_CTL),
+ IMX_PINCTRL_PIN(ENET2_RXC),
+ IMX_PINCTRL_PIN(ENET2_RD0),
+ IMX_PINCTRL_PIN(ENET2_RD1),
+ IMX_PINCTRL_PIN(ENET2_RD2),
+ IMX_PINCTRL_PIN(ENET2_RD3),
+ IMX_PINCTRL_PIN(SD1_CLK),
+ IMX_PINCTRL_PIN(SD1_CMD),
+ IMX_PINCTRL_PIN(SD1_DATA0),
+ IMX_PINCTRL_PIN(SD1_DATA1),
+ IMX_PINCTRL_PIN(SD1_DATA2),
+ IMX_PINCTRL_PIN(SD1_DATA3),
+ IMX_PINCTRL_PIN(SD1_DATA4),
+ IMX_PINCTRL_PIN(SD1_DATA5),
+ IMX_PINCTRL_PIN(SD1_DATA6),
+ IMX_PINCTRL_PIN(SD1_DATA7),
+ IMX_PINCTRL_PIN(SD1_STROBE),
+ IMX_PINCTRL_PIN(SD2_VSELECT),
+ IMX_PINCTRL_PIN(SD3_CLK),
+ IMX_PINCTRL_PIN(SD3_CMD),
+ IMX_PINCTRL_PIN(SD3_DATA0),
+ IMX_PINCTRL_PIN(SD3_DATA1),
+ IMX_PINCTRL_PIN(SD3_DATA2),
+ IMX_PINCTRL_PIN(SD3_DATA3),
+ IMX_PINCTRL_PIN(SD2_CD_B),
+ IMX_PINCTRL_PIN(SD2_CLK),
+ IMX_PINCTRL_PIN(SD2_CMD),
+ IMX_PINCTRL_PIN(SD2_DATA0),
+ IMX_PINCTRL_PIN(SD2_DATA1),
+ IMX_PINCTRL_PIN(SD2_DATA2),
+ IMX_PINCTRL_PIN(SD2_DATA3),
+ IMX_PINCTRL_PIN(SD2_RESET_B),
+ IMX_PINCTRL_PIN(I2C1_SCL),
+ IMX_PINCTRL_PIN(I2C1_SDA),
+ IMX_PINCTRL_PIN(I2C2_SCL),
+ IMX_PINCTRL_PIN(I2C2_SDA),
+ IMX_PINCTRL_PIN(UART1_RXD),
+ IMX_PINCTRL_PIN(UART1_TXD),
+ IMX_PINCTRL_PIN(UART2_RXD),
+ IMX_PINCTRL_PIN(UART2_TXD),
+ IMX_PINCTRL_PIN(PDM_CLK),
+ IMX_PINCTRL_PIN(PDM_BIT_STREAM0),
+ IMX_PINCTRL_PIN(PDM_BIT_STREAM1),
+ IMX_PINCTRL_PIN(SAI1_TXFS),
+ IMX_PINCTRL_PIN(SAI1_TXC),
+ IMX_PINCTRL_PIN(SAI1_TXD0),
+ IMX_PINCTRL_PIN(SAI1_RXD0),
+ IMX_PINCTRL_PIN(WDOG_ANY),
+};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx93.c b/drivers/pinctrl/nxp/pinctrl-imx93.c
index 5d250db1081..d13969856f6 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx93.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx93.c
@@ -1,34 +1,228 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2022 NXP
+ * Copyright 2026 NXP
*/
-#include <dm/device.h>
-#include <dm/pinctrl.h>
-
#include "pinctrl-imx.h"
-static struct imx_pinctrl_soc_info imx93_pinctrl_soc_info __section(".data") = {
- .flags = ZERO_OFFSET_VALID,
-};
-
-static const struct udevice_id imx93_pinctrl_match[] = {
- { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
- { .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
- { /* sentinel */ }
-};
-
-static const struct pinctrl_ops imx93_pinctrl_ops = {
- .set_state = imx_pinctrl_set_state_mmio,
+enum imx93_pads {
+ DAP_TDI = 0,
+ DAP_TMS_SWDIO = 1,
+ DAP_TCLK_SWCLK = 2,
+ DAP_TDO_TRACESWO = 3,
+ GPIO_IO00 = 4,
+ GPIO_IO01 = 5,
+ GPIO_IO02 = 6,
+ GPIO_IO03 = 7,
+ GPIO_IO04 = 8,
+ GPIO_IO05 = 9,
+ GPIO_IO06 = 10,
+ GPIO_IO07 = 11,
+ GPIO_IO08 = 12,
+ GPIO_IO09 = 13,
+ GPIO_IO10 = 14,
+ GPIO_IO11 = 15,
+ GPIO_IO12 = 16,
+ GPIO_IO13 = 17,
+ GPIO_IO14 = 18,
+ GPIO_IO15 = 19,
+ GPIO_IO16 = 20,
+ GPIO_IO17 = 21,
+ GPIO_IO18 = 22,
+ GPIO_IO19 = 23,
+ GPIO_IO20 = 24,
+ GPIO_IO21 = 25,
+ GPIO_IO22 = 26,
+ GPIO_IO23 = 27,
+ GPIO_IO24 = 28,
+ GPIO_IO25 = 29,
+ GPIO_IO26 = 30,
+ GPIO_IO27 = 31,
+ GPIO_IO28 = 32,
+ GPIO_IO29 = 33,
+ CCM_CLKO1 = 34,
+ CCM_CLKO2 = 35,
+ CCM_CLKO3 = 36,
+ CCM_CLKO4 = 37,
+ ENET1_MDC = 38,
+ ENET1_MDIO = 39,
+ ENET1_TD3 = 40,
+ ENET1_TD2 = 41,
+ ENET1_TD1 = 42,
+ ENET1_TD0 = 43,
+ ENET1_TX_CTL = 44,
+ ENET1_TXC = 45,
+ ENET1_RX_CTL = 46,
+ ENET1_RXC = 47,
+ ENET1_RD0 = 48,
+ ENET1_RD1 = 49,
+ ENET1_RD2 = 50,
+ ENET1_RD3 = 51,
+ ENET2_MDC = 52,
+ ENET2_MDIO = 53,
+ ENET2_TD3 = 54,
+ ENET2_TD2 = 55,
+ ENET2_TD1 = 56,
+ ENET2_TD0 = 57,
+ ENET2_TX_CTL = 58,
+ ENET2_TXC = 59,
+ ENET2_RX_CTL = 60,
+ ENET2_RXC = 61,
+ ENET2_RD0 = 62,
+ ENET2_RD1 = 63,
+ ENET2_RD2 = 64,
+ ENET2_RD3 = 65,
+ SD1_CLK = 66,
+ SD1_CMD = 67,
+ SD1_DATA0 = 68,
+ SD1_DATA1 = 69,
+ SD1_DATA2 = 70,
+ SD1_DATA3 = 71,
+ SD1_DATA4 = 72,
+ SD1_DATA5 = 73,
+ SD1_DATA6 = 74,
+ SD1_DATA7 = 75,
+ SD1_STROBE = 76,
+ SD2_VSELECT = 77,
+ SD3_CLK = 78,
+ SD3_CMD = 79,
+ SD3_DATA0 = 80,
+ SD3_DATA1 = 81,
+ SD3_DATA2 = 82,
+ SD3_DATA3 = 83,
+ SD2_CD_B = 84,
+ SD2_CLK = 85,
+ SD2_CMD = 86,
+ SD2_DATA0 = 87,
+ SD2_DATA1 = 88,
+ SD2_DATA2 = 89,
+ SD2_DATA3 = 90,
+ SD2_RESET_B = 91,
+ I2C1_SCL = 92,
+ I2C1_SDA = 93,
+ I2C2_SCL = 94,
+ I2C2_SDA = 95,
+ UART1_RXD = 96,
+ UART1_TXD = 97,
+ UART2_RXD = 98,
+ UART2_TXD = 99,
+ PDM_CLK = 100,
+ PDM_BIT_STREAM0 = 101,
+ PDM_BIT_STREAM1 = 102,
+ SAI1_TXFS = 103,
+ SAI1_TXC = 104,
+ SAI1_TXD0 = 105,
+ SAI1_RXD0 = 106,
+ WDOG_ANY = 107,
};
-U_BOOT_DRIVER(imx93_pinctrl) = {
- .name = "imx93-pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = of_match_ptr(imx93_pinctrl_match),
- .probe = imx_pinctrl_probe_mmio,
- .remove = imx_pinctrl_remove_mmio,
- .priv_auto = sizeof(struct imx_pinctrl_priv),
- .ops = &imx93_pinctrl_ops,
- .flags = DM_FLAG_PRE_RELOC,
+static const struct imx_pinctrl_pin_desc imx9_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(DAP_TDI),
+ IMX_PINCTRL_PIN(DAP_TMS_SWDIO),
+ IMX_PINCTRL_PIN(DAP_TCLK_SWCLK),
+ IMX_PINCTRL_PIN(DAP_TDO_TRACESWO),
+ IMX_PINCTRL_PIN(GPIO_IO00),
+ IMX_PINCTRL_PIN(GPIO_IO01),
+ IMX_PINCTRL_PIN(GPIO_IO02),
+ IMX_PINCTRL_PIN(GPIO_IO03),
+ IMX_PINCTRL_PIN(GPIO_IO04),
+ IMX_PINCTRL_PIN(GPIO_IO05),
+ IMX_PINCTRL_PIN(GPIO_IO06),
+ IMX_PINCTRL_PIN(GPIO_IO07),
+ IMX_PINCTRL_PIN(GPIO_IO08),
+ IMX_PINCTRL_PIN(GPIO_IO09),
+ IMX_PINCTRL_PIN(GPIO_IO10),
+ IMX_PINCTRL_PIN(GPIO_IO11),
+ IMX_PINCTRL_PIN(GPIO_IO12),
+ IMX_PINCTRL_PIN(GPIO_IO13),
+ IMX_PINCTRL_PIN(GPIO_IO14),
+ IMX_PINCTRL_PIN(GPIO_IO15),
+ IMX_PINCTRL_PIN(GPIO_IO16),
+ IMX_PINCTRL_PIN(GPIO_IO17),
+ IMX_PINCTRL_PIN(GPIO_IO18),
+ IMX_PINCTRL_PIN(GPIO_IO19),
+ IMX_PINCTRL_PIN(GPIO_IO20),
+ IMX_PINCTRL_PIN(GPIO_IO21),
+ IMX_PINCTRL_PIN(GPIO_IO22),
+ IMX_PINCTRL_PIN(GPIO_IO23),
+ IMX_PINCTRL_PIN(GPIO_IO24),
+ IMX_PINCTRL_PIN(GPIO_IO25),
+ IMX_PINCTRL_PIN(GPIO_IO26),
+ IMX_PINCTRL_PIN(GPIO_IO27),
+ IMX_PINCTRL_PIN(GPIO_IO28),
+ IMX_PINCTRL_PIN(GPIO_IO29),
+ IMX_PINCTRL_PIN(CCM_CLKO1),
+ IMX_PINCTRL_PIN(CCM_CLKO2),
+ IMX_PINCTRL_PIN(CCM_CLKO3),
+ IMX_PINCTRL_PIN(CCM_CLKO4),
+ IMX_PINCTRL_PIN(ENET1_MDC),
+ IMX_PINCTRL_PIN(ENET1_MDIO),
+ IMX_PINCTRL_PIN(ENET1_TD3),
+ IMX_PINCTRL_PIN(ENET1_TD2),
+ IMX_PINCTRL_PIN(ENET1_TD1),
+ IMX_PINCTRL_PIN(ENET1_TD0),
+ IMX_PINCTRL_PIN(ENET1_TX_CTL),
+ IMX_PINCTRL_PIN(ENET1_TXC),
+ IMX_PINCTRL_PIN(ENET1_RX_CTL),
+ IMX_PINCTRL_PIN(ENET1_RXC),
+ IMX_PINCTRL_PIN(ENET1_RD0),
+ IMX_PINCTRL_PIN(ENET1_RD1),
+ IMX_PINCTRL_PIN(ENET1_RD2),
+ IMX_PINCTRL_PIN(ENET1_RD3),
+ IMX_PINCTRL_PIN(ENET2_MDC),
+ IMX_PINCTRL_PIN(ENET2_MDIO),
+ IMX_PINCTRL_PIN(ENET2_TD3),
+ IMX_PINCTRL_PIN(ENET2_TD2),
+ IMX_PINCTRL_PIN(ENET2_TD1),
+ IMX_PINCTRL_PIN(ENET2_TD0),
+ IMX_PINCTRL_PIN(ENET2_TX_CTL),
+ IMX_PINCTRL_PIN(ENET2_TXC),
+ IMX_PINCTRL_PIN(ENET2_RX_CTL),
+ IMX_PINCTRL_PIN(ENET2_RXC),
+ IMX_PINCTRL_PIN(ENET2_RD0),
+ IMX_PINCTRL_PIN(ENET2_RD1),
+ IMX_PINCTRL_PIN(ENET2_RD2),
+ IMX_PINCTRL_PIN(ENET2_RD3),
+ IMX_PINCTRL_PIN(SD1_CLK),
+ IMX_PINCTRL_PIN(SD1_CMD),
+ IMX_PINCTRL_PIN(SD1_DATA0),
+ IMX_PINCTRL_PIN(SD1_DATA1),
+ IMX_PINCTRL_PIN(SD1_DATA2),
+ IMX_PINCTRL_PIN(SD1_DATA3),
+ IMX_PINCTRL_PIN(SD1_DATA4),
+ IMX_PINCTRL_PIN(SD1_DATA5),
+ IMX_PINCTRL_PIN(SD1_DATA6),
+ IMX_PINCTRL_PIN(SD1_DATA7),
+ IMX_PINCTRL_PIN(SD1_STROBE),
+ IMX_PINCTRL_PIN(SD2_VSELECT),
+ IMX_PINCTRL_PIN(SD3_CLK),
+ IMX_PINCTRL_PIN(SD3_CMD),
+ IMX_PINCTRL_PIN(SD3_DATA0),
+ IMX_PINCTRL_PIN(SD3_DATA1),
+ IMX_PINCTRL_PIN(SD3_DATA2),
+ IMX_PINCTRL_PIN(SD3_DATA3),
+ IMX_PINCTRL_PIN(SD2_CD_B),
+ IMX_PINCTRL_PIN(SD2_CLK),
+ IMX_PINCTRL_PIN(SD2_CMD),
+ IMX_PINCTRL_PIN(SD2_DATA0),
+ IMX_PINCTRL_PIN(SD2_DATA1),
+ IMX_PINCTRL_PIN(SD2_DATA2),
+ IMX_PINCTRL_PIN(SD2_DATA3),
+ IMX_PINCTRL_PIN(SD2_RESET_B),
+ IMX_PINCTRL_PIN(I2C1_SCL),
+ IMX_PINCTRL_PIN(I2C1_SDA),
+ IMX_PINCTRL_PIN(I2C2_SCL),
+ IMX_PINCTRL_PIN(I2C2_SDA),
+ IMX_PINCTRL_PIN(UART1_RXD),
+ IMX_PINCTRL_PIN(UART1_TXD),
+ IMX_PINCTRL_PIN(UART2_RXD),
+ IMX_PINCTRL_PIN(UART2_TXD),
+ IMX_PINCTRL_PIN(PDM_CLK),
+ IMX_PINCTRL_PIN(PDM_BIT_STREAM0),
+ IMX_PINCTRL_PIN(PDM_BIT_STREAM1),
+ IMX_PINCTRL_PIN(SAI1_TXFS),
+ IMX_PINCTRL_PIN(SAI1_TXC),
+ IMX_PINCTRL_PIN(SAI1_TXD0),
+ IMX_PINCTRL_PIN(SAI1_RXD0),
+ IMX_PINCTRL_PIN(WDOG_ANY),
};
generated by cgit v1.2.3 (git 2.25.1) at 2026-08-05 23:03:20 +0000