diff options
Diffstat (limited to 'arch/arm/mach-stm32mp/stm32mp2')
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/cpu.c | 20 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/rifsc.c | 37 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/stm32mp21x.c | 148 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c | 44 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c | 46 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/stm32mp2x.c | 63 |
8 files changed, 245 insertions, 117 deletions
diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile index 27fbf3ae728..8f2e641dcab 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -6,6 +6,8 @@ obj-y += cpu.o obj-y += arm64-mmu.o obj-y += rifsc.o +obj-y += stm32mp2x.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o +obj-$(CONFIG_STM32MP21X) += stm32mp21x.o obj-$(CONFIG_STM32MP23X) += stm32mp23x.o obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c index 36c631ef0c2..4f418b65d38 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c +++ b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c @@ -16,6 +16,7 @@ struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = { { +#if defined(CONFIG_STM32MP25X) /* PCIe */ .virt = 0x10000000UL, .phys = 0x10000000UL, @@ -24,6 +25,7 @@ struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { +#endif /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */ .virt = 0x20000000UL, .phys = 0x20000000UL, diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c index e081dc605b8..5e2ecb93ee4 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@ -15,6 +15,7 @@ #include <asm/io.h> #include <asm/arch/stm32.h> #include <asm/arch/sys_proto.h> +#include <asm/armv8/mmu.h> #include <asm/system.h> #include <dm/device.h> #include <dm/lists.h> @@ -70,8 +71,21 @@ int mach_cpu_init(void) void enable_caches(void) { + struct mm_region *mem = mem_map; + /* deactivate the data cache, early enabled in arch_cpu_init() */ dcache_disable(); + + /* Parse mem_map and find DDR entry */ + while (mem->size) { + if (mem->phys == CONFIG_TEXT_BASE) { + /* update DDR entry with real DDR size */ + mem->size = gd->ram_size; + break; + } + mem++; + } + /* * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr * to update the TLB location udpated in board_f.c::reserve_mmu @@ -128,8 +142,10 @@ static void setup_boot_mode(void) STM32_UART5_BASE, STM32_USART6_BASE, STM32_UART7_BASE, +#ifdef CONFIG_STM32MP25X STM32_UART8_BASE, STM32_UART9_BASE +#endif }; const u32 sdmmc_addr[] = { STM32_SDMMC1_BASE, @@ -148,7 +164,7 @@ static void setup_boot_mode(void) __func__, boot_ctx, boot_mode, instance, forced_mode); switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { case BOOT_SERIAL_UART: - if (instance > ARRAY_SIZE(serial_addr)) + if (instance >= ARRAY_SIZE(serial_addr)) break; /* serial : search associated node in devicetree */ sprintf(cmd, "serial@%x", serial_addr[instance]); @@ -178,7 +194,7 @@ static void setup_boot_mode(void) break; case BOOT_FLASH_SD: case BOOT_FLASH_EMMC: - if (instance > ARRAY_SIZE(sdmmc_addr)) + if (instance >= ARRAY_SIZE(sdmmc_addr)) break; /* search associated sdmmc node in devicetree */ sprintf(cmd, "mmc@%x", sdmmc_addr[instance]); diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c index f8f67af4449..9db8b9efc64 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c +++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c @@ -141,27 +141,16 @@ static int rifsc_check_access(void *base, u32 id) cid_reg_value = readl(base + RIFSC_RISC_PER0_CIDCFGR(id)); sem_reg_value = readl(base + RIFSC_RISC_PER0_SEMCR(id)); - /* - * First check conditions for semaphore mode, which doesn't take into - * account static CID. - */ - if (cid_reg_value & CIDCFGR_SEMEN) - goto skip_cid_check; - - /* - * Skip cid check if CID filtering isn't enabled or filtering is enabled on CID0, which - * corresponds to whatever CID. - */ - if (!(cid_reg_value & CIDCFGR_CFEN) || - FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0) - goto skip_cid_check; - - /* Coherency check with the CID configuration */ - if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) { - log_debug("Invalid CID configuration for peripheral %d\n", id); + /* Check security configuration */ + if (sec_reg_value & BIT(reg_offset)) { + log_debug("Invalid security configuration for peripheral %d\n", id); return -EACCES; } + /* Skip cid check if CID filtering isn't enabled */ + if (!(cid_reg_value & CIDCFGR_CFEN)) + goto skip_cid_check; + /* Check semaphore accesses */ if (cid_reg_value & CIDCFGR_SEMEN) { if (!(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { @@ -173,15 +162,12 @@ static int rifsc_check_access(void *base, u32 id) log_debug("Semaphore unavailable for peripheral %d\n", id); return -EACCES; } - } - -skip_cid_check: - /* Check security configuration */ - if (sec_reg_value & BIT(reg_offset)) { - log_debug("Invalid security configuration for peripheral %d\n", id); + } else if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) { + log_debug("Invalid CID configuration for peripheral %d\n", id); return -EACCES; } +skip_cid_check: return 0; } @@ -208,7 +194,7 @@ int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id) * If the peripheral is in semaphore mode, take the semaphore so that * the CID1 has the ownership. */ - if (cid_reg_value & CIDCFGR_SEMEN && + if (cid_reg_value & CIDCFGR_CFEN && cid_reg_value & CIDCFGR_SEMEN && (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { err = stm32_rifsc_acquire_semaphore(rifsc_base, id); if (err) { @@ -367,6 +353,7 @@ static int stm32_rifsc_remove(struct udevice *bus) } static const struct udevice_id stm32_rifsc_ids[] = { + { .compatible = "st,stm32mp21-rifsc" }, { .compatible = "st,stm32mp25-rifsc" }, {}, }; diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp21x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp21x.c new file mode 100644 index 00000000000..7b5d79d3497 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp21x.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2026, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> + +/* Package = bit 0:2 of OTP122 => STM32MP21_PKG defines + * - 000: Custom package + * - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 011: VFBGA273 => AN = 11x11, 273 balls pith 0.5mm + * - 100: VFBGA225 => AO = 8x8, 225 balls pith 0.5mm + * - 101: TFBGA289 => AM = 14x14, 289 balls pith 0.8mm + * - others: Reserved + */ + +int get_eth_nb(void) +{ + int nb_eth; + + switch (get_cpu_type()) { + case CPU_STM32MP215Axx: + fallthrough; + case CPU_STM32MP215Cxx: + fallthrough; + case CPU_STM32MP215Dxx: + fallthrough; + case CPU_STM32MP215Fxx: + fallthrough; + case CPU_STM32MP213Axx: + fallthrough; + case CPU_STM32MP213Cxx: + fallthrough; + case CPU_STM32MP213Dxx: + fallthrough; + case CPU_STM32MP213Fxx: + nb_eth = 2; /* dual ETH */ + break; + case CPU_STM32MP211Axx: + fallthrough; + case CPU_STM32MP211Cxx: + fallthrough; + case CPU_STM32MP211Dxx: + fallthrough; + case CPU_STM32MP211Fxx: + nb_eth = 1; /* single ETH */ + break; + default: + nb_eth = 0; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r, *package; + + cpu_s = "????"; + cpu_r = "?"; + package = "??"; + if (get_cpu_dev() == CPU_DEV_STM32MP21) { + switch (get_cpu_type()) { + case CPU_STM32MP215Fxx: + cpu_s = "215F"; + break; + case CPU_STM32MP215Dxx: + cpu_s = "215D"; + break; + case CPU_STM32MP215Cxx: + cpu_s = "215C"; + break; + case CPU_STM32MP215Axx: + cpu_s = "215A"; + break; + case CPU_STM32MP213Fxx: + cpu_s = "213F"; + break; + case CPU_STM32MP213Dxx: + cpu_s = "213D"; + break; + case CPU_STM32MP213Cxx: + cpu_s = "213C"; + break; + case CPU_STM32MP213Axx: + cpu_s = "213A"; + break; + case CPU_STM32MP211Fxx: + cpu_s = "211F"; + break; + case CPU_STM32MP211Dxx: + cpu_s = "211D"; + break; + case CPU_STM32MP211Cxx: + cpu_s = "211C"; + break; + case CPU_STM32MP211Axx: + cpu_s = "211A"; + break; + default: + cpu_s = "21??"; + break; + } + /* REVISION */ + switch (get_cpu_rev()) { + case OTP_REVID_1: + cpu_r = "A"; + break; + case OTP_REVID_1_1: + cpu_r = "Z"; + break; + case OTP_REVID_2: + cpu_r = "B"; + break; + default: + break; + } + /* PACKAGE */ + switch (get_cpu_package()) { + case STM32MP25_PKG_CUSTOM: + package = "XX"; + break; + case STM32MP21_PKG_AL_VFBGA361: + package = "AL"; + break; + case STM32MP21_PKG_AN_VFBGA273: + package = "AN"; + break; + case STM32MP21_PKG_AO_VFBGA225: + package = "AO"; + break; + case STM32MP21_PKG_AM_TFBGA289: + package = "AM"; + break; + default: + break; + } + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c index 022db60811a..e4e5812760c 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c @@ -11,19 +11,6 @@ #include <asm/arch/stm32.h> #include <asm/arch/sys_proto.h> -/* SYSCFG register */ -#define SYSCFG_DEVICEID_OFFSET 0x6400 -#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) -#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 - -/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/ -#define REVID_SHIFT 0 -#define REVID_MASK GENMASK(5, 0) - -/* Device Part Number (RPN) = OTP9 */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(31, 0) - /* Package = bit 0:2 of OTP122 => STM32MP23_PKG defines * - 000: Custom package * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm @@ -31,37 +18,6 @@ * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm * - others: Reserved */ -#define PKG_SHIFT 0 -#define PKG_MASK GENMASK(2, 0) - -static u32 read_deviceid(void) -{ - void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); - - return readl(syscfg + SYSCFG_DEVICEID_OFFSET); -} - -u32 get_cpu_dev(void) -{ - return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; -} - -u32 get_cpu_rev(void) -{ - return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK); -} - -/* Get Device Part Number (RPN) from OTP */ -u32 get_cpu_type(void) -{ - return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); -} - -/* Get Package options from OTP */ -u32 get_cpu_package(void) -{ - return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); -} int get_eth_nb(void) { diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c index bf1f3d3c5a7..e0d54f4ecc8 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c @@ -6,24 +6,9 @@ #define LOG_CATEGORY LOGC_ARCH #include <log.h> -#include <syscon.h> #include <asm/io.h> -#include <asm/arch/stm32.h> #include <asm/arch/sys_proto.h> -/* SYSCFG register */ -#define SYSCFG_DEVICEID_OFFSET 0x6400 -#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) -#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 - -/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/ -#define REVID_SHIFT 0 -#define REVID_MASK GENMASK(5, 0) - -/* Device Part Number (RPN) = OTP9 */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(31, 0) - /* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines * - 000: Custom package * - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm @@ -31,37 +16,6 @@ * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm * - others: Reserved */ -#define PKG_SHIFT 0 -#define PKG_MASK GENMASK(2, 0) - -static u32 read_deviceid(void) -{ - void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); - - return readl(syscfg + SYSCFG_DEVICEID_OFFSET); -} - -u32 get_cpu_dev(void) -{ - return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; -} - -u32 get_cpu_rev(void) -{ - return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK); -} - -/* Get Device Part Number (RPN) from OTP */ -u32 get_cpu_type(void) -{ - return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); -} - -/* Get Package options from OTP */ -u32 get_cpu_package(void) -{ - return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); -} int get_eth_nb(void) { diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp2x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp2x.c new file mode 100644 index 00000000000..40fceac402c --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp2x.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2026, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <linux/err.h> + +/* SYSCFG register */ +#define SYSCFG_DEVICEID_OFFSET 0x6400 +#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 + +/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/ +#define REVID_SHIFT 0 +#define REVID_MASK GENMASK(5, 0) + +/* Device Part Number (RPN) = OTP9 */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(31, 0) + +#define PKG_SHIFT 0 +#define PKG_MASK GENMASK(2, 0) + +static u32 read_deviceid(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + if (IS_ERR(syscfg)) { + pr_err("Error, can't get SYSCON range (%ld)\n", PTR_ERR(syscfg)); + + return PTR_ERR(syscfg); + } + + return readl(syscfg + SYSCFG_DEVICEID_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK); +} + +/* Get Device Part Number (RPN) from OTP */ +u32 get_cpu_type(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} |