diff options
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/imx8-capricorn-cxg3.dts | 44 | ||||
| -rw-r--r-- | arch/arm/dts/imx8-capricorn.dtsi | 60 |
2 files changed, 45 insertions, 59 deletions
diff --git a/arch/arm/dts/imx8-capricorn-cxg3.dts b/arch/arm/dts/imx8-capricorn-cxg3.dts index 2f8597579f3..b40410b2b6f 100644 --- a/arch/arm/dts/imx8-capricorn-cxg3.dts +++ b/arch/arm/dts/imx8-capricorn-cxg3.dts @@ -102,6 +102,26 @@ pinctrl-0 = <&pinctrl_gpio_keys>; muxcgrp: imx8qxp-som { + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 + + SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + >; + }; + pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 @@ -127,3 +147,27 @@ >; }; }; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rmii"; + + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/dts/imx8-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi index 3734a9d21f1..f640daa775f 100644 --- a/arch/arm/dts/imx8-capricorn.dtsi +++ b/arch/arm/dts/imx8-capricorn.dtsi @@ -63,41 +63,6 @@ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 - SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 - SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 - SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 - SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 - SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 - SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 - SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021 - //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 - SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021 - >; - }; - - pinctrl_fec2: fec2grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 - - SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 - SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 - - SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 - SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 - SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 - SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 - SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 - SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 - SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 - SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */ >; }; }; @@ -126,6 +91,7 @@ &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; + max-frequency = <52000000>; clock-frequency=<52000000>; no-1-8-v; bus-width = <8>; @@ -160,27 +126,3 @@ &fec1 { status ="disabled"; }; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rmii"; - - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; |