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|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
The QMP PHY controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,kaanapali-qmp-usb3-dp-phy
- const: qcom,sm8750-qmp-usb3-dp-phy
- enum:
- qcom,glymur-qmp-usb3-dp-phy
- qcom,sar2130p-qmp-usb3-dp-phy
- qcom,sc7180-qmp-usb3-dp-phy
- qcom,sc7280-qmp-usb3-dp-phy
- qcom,sc8180x-qmp-usb3-dp-phy
- qcom,sc8280xp-qmp-usb43dp-phy
- qcom,sdm845-qmp-usb3-dp-phy
- qcom,sm6350-qmp-usb3-dp-phy
- qcom,sm8150-qmp-usb3-dp-phy
- qcom,sm8250-qmp-usb3-dp-phy
- qcom,sm8350-qmp-usb3-dp-phy
- qcom,sm8450-qmp-usb3-dp-phy
- qcom,sm8550-qmp-usb3-dp-phy
- qcom,sm8650-qmp-usb3-dp-phy
- qcom,sm8750-qmp-usb3-dp-phy
- qcom,x1e80100-qmp-usb3-dp-phy
reg:
maxItems: 1
clocks:
minItems: 4
maxItems: 5
clock-names:
minItems: 4
items:
- const: aux
- const: ref
- const: com_aux
- const: usb3_pipe
- const: cfg_ahb
power-domains:
maxItems: 1
resets:
maxItems: 2
reset-names:
items:
- const: phy
- const: common
vdda-phy-supply: true
vdda-pll-supply: true
refgen-supply: true
"#clock-cells":
const: 1
description:
See include/dt-bindings/phy/phy-qcom-qmp.h
"#phy-cells":
const: 1
description:
See include/dt-bindings/phy/phy-qcom-qmp.h
mode-switch: true
orientation-switch: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
description: Output endpoint of the PHY
unevaluatedProperties: false
properties:
endpoint:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
unevaluatedProperties: false
endpoint@0:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
description: Display Port Output lanes of the PHY when used with static mapping,
The entry index is the DP lanes index, and the number is the PHY
signal in the order RX0, TX0, TX1, RX1.
unevaluatedProperties: false
properties:
# Static lane mappings are mutually exclusive with typec-mux/orientation-mux
data-lanes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 4
oneOf:
- items: # DisplayPort 1 lane, normal orientation
- const: 3
- items: # DisplayPort 1 lane, flipped orientation
- const: 0
- items: # DisplayPort 2 lanes, normal orientation
- const: 3
- const: 2
- items: # DisplayPort 2 lanes, flipped orientation
- const: 0
- const: 1
- items: # DisplayPort 4 lanes, normal orientation
- const: 3
- const: 2
- const: 1
- const: 0
- items: # DisplayPort 4 lanes, flipped orientation
- const: 0
- const: 1
- const: 2
- const: 3
required:
- data-lanes
endpoint@1:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
description: USB Output lanes of the PHY when used with static mapping.
The entry index is the USB3 lane in the order TX then RX, and the
number is the PHY signal in the order RX0, TX0, TX1, RX1.
unevaluatedProperties: false
properties:
# Static lane mappings are mutually exclusive with typec-mux/orientation-mux
data-lanes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
oneOf:
- items: # USB3, normal orientation
- const: 1
- const: 0
- items: # USB3, flipped orientation
- const: 2
- const: 3
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Incoming endpoint from the USB controller
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: Incoming endpoint from the DisplayPort controller
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- vdda-phy-supply
- vdda-pll-supply
- "#clock-cells"
- "#phy-cells"
allOf:
- $ref: /schemas/usb/usb-switch.yaml#
- if:
properties:
compatible:
enum:
- qcom,sc7180-qmp-usb3-dp-phy
- qcom,sdm845-qmp-usb3-dp-phy
then:
properties:
clocks:
maxItems: 5
clock-names:
maxItems: 5
else:
properties:
clocks:
maxItems: 4
clock-names:
maxItems: 4
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-qmp-usb3-dp-phy
- qcom,sar2130p-qmp-usb3-dp-phy
- qcom,sc8280xp-qmp-usb43dp-phy
- qcom,sm6350-qmp-usb3-dp-phy
- qcom,sm8550-qmp-usb3-dp-phy
- qcom,sm8650-qmp-usb3-dp-phy
- qcom,sm8750-qmp-usb3-dp-phy
- qcom,x1e80100-qmp-usb3-dp-phy
then:
required:
- power-domains
else:
properties:
power-domains: false
- if:
properties:
compatible:
enum:
- qcom,glymur-qmp-usb3-dp-phy
then:
required:
- refgen-supply
else:
properties:
refgen-supply: false
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
phy@88eb000 {
compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
reg = <0x088eb000 0x4000>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB4_EUD_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "aux", "ref", "com_aux", "usb3_pipe";
power-domains = <&gcc USB30_PRIM_GDSC>;
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
vdda-phy-supply = <&vreg_l9d>;
vdda-pll-supply = <&vreg_l4d>;
orientation-switch;
#clock-cells = <1>;
#phy-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&typec_connector_ss>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&dwc3_ss_out>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&mdss_dp_out>;
};
};
};
};
|
