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2026-02-06Merge tag 'drm-intel-next-fixes-2026-02-05' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next - Fix the pixel normalization handling for xe3p_lpd display Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patch.msgid.link/aYROngKfyUIyoQW0@jlahtine-mobl
2026-02-02drm/i915/display: fix the pixel normalization handling for xe3p_lpdVinod Govindapillai
Pixel normalizer is enabled with normalization factor as 1.0 for FP16 formats in order to support FBC for those formats in xe3p_lpd. Previously pixel normalizer gets disabled during the plane disable routine. But there could be plane format settings without explicitly calling the plane disable in-between and we could endup keeping the pixel normalizer enabled for formats which we don't require that. This is causing crc mismatches in yuv formats and FIFO underruns in planar formats like NV12. Fix this by updating the pixel normalizer configuration based on the pixel formats explicitly during the plane settings arm calls itself - enable it for FP16 and disable it for other formats in HDR capable planes. v2: avoid redundant pixel normalization setting updates v3: moved the normalization factor definition to intel_fbc.c and some updates to comments v4: simplified the pixel normalizer setting handling Fixes: 5298eea7ed20 ("drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBC") Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20260130095919.107805-1-vinod.govindapillai@intel.com (cherry picked from commit c0dc68f4e2aa7eddb9ec6d95931f9576d8fe7334) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2026-01-30Merge tag 'drm-intel-next-fixes-2026-01-29' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next - Prevent u64 underflow in intel_fbc_stolen_end Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patch.msgid.link/aXsWGWjacEJ03rTs@jlahtine-mobl
2026-01-28BackMerge tag 'v6.19-rc7' into drm-nextDave Airlie
Linux 6.19-rc7 This is needed for msm and rust trees. Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-01-26drm/i915/display: Prevent u64 underflow in intel_fbc_stolen_endJonathan Cavitt
Static analysis reveals a potential integer underflow in intel_fbc_stolen_end. This can apparently occur if intel_parent_stolen_area_size returns zero (or, theoretically, any value less than 2^23), as 2^23 is subtracted from the return value and stored in a u64. While this doesn't appear to cause any issues due to the use of the min() function to clamp the return values from the intel_fbc_stolen_end function, it would be best practice to avoid undeflowing values like this on principle. So, rework the function to prevent the underflow from occurring. Note that the underflow at present would result in the value of intel_fbc_cfb_base_max being returned at the end of intel_fbc_stolen_end, so just return that if the value of intel_parent_stolen_area_size is too small. While we're here, fix the other comments here and modify the execution path for readability. v2: (Jani) - Fix the comments in intel_fbc_stolen_end - Use check_sub_overflow - Remove macro that mirrors SZ_8M, as it is now only referenced once - Misc. formatting fixes Fixes: a9da512b3ed7 ("drm/i915: avoid the last 8mb of stolen on BDW/SKL") Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260107162935.8123-2-jonathan.cavitt@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> (cherry picked from commit 6695dc279820a50cb20ecd8b5250e05234dac780) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2026-01-22drm/i915/display: Fix color pipeline enum name leakChaitanya Kumar Borah
intel_color_pipeline_plane_init() allocates enum names for color pipelines, which are copied by drm_property_create_enum(). The temporary strings were not freed, resulting in a memory leak. Allocate enum names only after successful pipeline construction and free them on all exit paths. Fixes: ef105316819d ("drm/i915/color: Create a transfer function color pipeline") Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260113102303.724205-5-chaitanya.kumar.borah@intel.com
2026-01-22drm/i915/color: Place 3D LUT after CSC in plane color pipelineChaitanya Kumar Borah
Move the 3D LUT block to its correct position in the plane color pipeline: [Pre-CSC] -> [CSC] -> [3DLUT] -> [Post-CSC] Fixes: 65db7a1f9cf7 ("drm/i915/color: Add 3D LUT to color pipeline") Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260113102303.724205-2-chaitanya.kumar.borah@intel.com
2026-01-19drm/i915/psr: Don't enable Panel Replay on sink if globally disabledJouni Högander
With some panels informing support for Panel Replay we are observing problems if having Panel Replay enable bit set on sink when forced to use PSR instead of Panel Replay. Avoid these problems by not setting Panel Replay enable bit in sink when Panel Replay is globally disabled during link training. I.e. disabled by module parameter. The enable bit is still set when disabling Panel Replay via debugfs interface. Added note comment about this. Fixes: 68f3a505b367 ("drm/i915/psr: Enable Panel Replay on sink always when it's supported") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: <stable@vger.kernel.org> # v6.15+ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patch.msgid.link/20260115070039.368965-1-jouni.hogander@intel.com (cherry picked from commit c5a52cd04e24f0ae53fda26f74ab027b8c548e0e) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2026-01-16Merge tag 'drm-intel-next-2026-01-15' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Beyond Display: - Make 'guc_hw_reg_state' static as it isn't exported (Ben) - Fix doc build on mei related interface header (Jani) Display related: - Fix ggtt fb alignment on Xe display (Tvrtko) - More display clean-up towards deduplication and full separation (Jani) - Use the consolidated HDMI tables (Suraj) - Account for DSC slice overhead (Ankit) - Prepare GVT for display modularization (Ankit, Jani) - Enable/Disable DC balance along with VRR DSB (Mitul, Ville) - Protection against unsupported modes in LT PHY (Suraj) - Display W/a addition and fixes (Gustavo) - Fix many SPDX identifier comments (Ankit) - Incorporate Xe3_LPD changes for CD2X divider (Gustavo) - Clean up link BW/DSC slice config computation (Imre) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/aWkNThVRSkGAfUVv@intel.com
2026-01-13drm/i915/dp: Simplify computing the DSC compressed BPP for DP-MSTImre Deak
The minimum/maximum DSC input (i.e. pipe) and compressed (i.e. link) BPP limits are computed already in intel_dp_compute_config_limits(), so there is no need to do this again in mst_stream_dsc_compute_link_config() called later. Remove the corresponding alignments from the latter function and use the precomputed (aligned and within bounds) maximum pipe BPP and the min/max compressed BPP values instead as-is. Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-21-imre.deak@intel.com
2026-01-13drm/i915/dp: Simplify eDP vs. DP compressed BPP computationImre Deak
intel_edp_dsc_compute_pipe_bpp() matches now intel_dp_dsc_compute_pipe_bpp(), remove the former function. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-20-imre.deak@intel.com
2026-01-13drm/i915/dp: Unify computing compressed BPP for DP-SST and eDPImre Deak
Move computing the eDP compressed BPP value to the function computing this for DP, allowing further simplifications later. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-19-imre.deak@intel.com
2026-01-13drm/i915/dp: Simplify computing forced DSC BPP for DP-SSTImre Deak
If dsc_compute_compressed_bpp() failed with a forced pipe BPP value (where the forced pipe BPP value itself is valid within the min/max pipe BPP limits), the function will also fail when called with the maximum pipe BPP value: dsc_compute_compressed_bpp() will try all compressed BPPs below the passed in pipe BPP value and if the function failed with a given (low) compressed BPP value it will also fail with a compressed BPP value higher than the one which failed already. Based on the above remove the logic to retry computing a compressed BPP value with the maximum pipe BPP value if computing the compressed BPP failed already with the (lower) forced pipe BPP value. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-18-imre.deak@intel.com
2026-01-13drm/i915/dp: Simplify computing DSC BPPs for DP-SSTImre Deak
The maximum pipe BPP value (used as the DSC input BPP) has been aligned already to the corresponding source/sink input BPP capabilities in intel_dp_compute_config_limits(). So it isn't needed to perform the same alignment again in intel_dp_dsc_compute_pipe_bpp() called later, this function can simply use the already aligned maximum pipe BPP value, do that. Also, there is no point in trying pipe BPP values lower than the maximum: this would only make dsc_compute_compressed_bpp() start with a lower _compressed_ BPP value, but this lower compressed BPP value has been tried already when dsc_compute_compressed_bpp() was called with the higher pipe BPP value (i.e. the first dsc_compute_compressed_bpp() call tries already all the possible compressed BPP values which are all below the pipe BPP value passed to it). Simplify the function accordingly trying only the maximum pipe BPP value. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-17-imre.deak@intel.com
2026-01-13drm/i915/dp: Simplify computing DSC BPPs for eDPImre Deak
The maximum pipe BPP value (used as the DSC input BPP) has been aligned already to the corresponding source/sink input BPP capabilities in intel_dp_compute_config_limits(). So it isn't needed to perform the same alignment again in intel_edp_dsc_compute_pipe_bpp() called later, this function can simply use the already aligned maximum pipe BPP value, do that. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-16-imre.deak@intel.com
2026-01-13drm/i915/dp: Use helpers to align min/max compressed BPPsImre Deak
The minimum/maximum compressed BPP values are aligned/bounded in intel_dp_compute_link_bpp_limits() to the corresponding source limits. The minimum compressed BPP value doesn't change afterwards, so no need to align it again, remove that. The maximum compressed BPP, which depends on the pipe BPP value still needs to be aligned, since the pipe BPP value could change after the above limits were computed, via intel_dp_force_dsc_pipe_bpp(). Use the corresponding helper for this alignment instead of open-coding the same. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-15-imre.deak@intel.com
2026-01-13drm/i915/dp: Unify detect and compute time DSC mode BW validationImre Deak
Atm, a DP DSC video mode's required BW vs. the available BW is determined by calculating the maximum compressed BPP value allowed by the available BW. Doing that using a closed-form formula as it's done atm (vs. an iterative way) is problematic, since the overhead of the required BW itself depends on the BPP value being calculated. Instead of that calculate the required BW for the minimum compressed BPP value supported both by the source and the sink and check this BW against the available BW. This change also aligns the BW calculation during mode validation with how this is done during state computation, calculating the required effective data rate with the corresponding BW overhead. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-14-imre.deak@intel.com
2026-01-13drm/i915/dp: Add intel_dp_mode_valid_with_dsc()Imre Deak
Add intel_dp_mode_valid_with_dsc() and call this for an SST/MST mode validation to prepare for a follow-up change using a way to verify the mode's required BW the same way this is done elsewhere during state computation (which in turn depends on the mode's effective data rate with the corresponding BW overhead). Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-13-imre.deak@intel.com
2026-01-13drm/i915/dp: Factor out compute_max_compressed_bpp_x16()Imre Deak
Factor out compute_max_compressed_bpp_x16() also used during mode validation in a follow-up change. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-12-imre.deak@intel.com
2026-01-13drm/i915/dp: Factor out compute_min_compressed_bpp_x16()Imre Deak
Factor out compute_min_compressed_bpp_x16() also used during mode validation in a follow-up change. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-11-imre.deak@intel.com
2026-01-13drm/i915/dp: Pass mode clock to dsc_throughput_quirk_max_bpp_x16()Imre Deak
Prepare for follow-up changes using dsc_throughput_quirk_max_bpp_x16() without an intel_crtc_state pointer. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-10-imre.deak@intel.com
2026-01-13drm/i915/dp: Pass intel_output_format to ↵Imre Deak
intel_dp_dsc_sink_{min_max}_compressed_bpp() Prepare for follow-up changes also calling intel_dp_dsc_min_sink_compressed_bpp() / intel_dp_dsc_max_sink_compressed_bpp_x16() without an intel_crtc_state. While at it remove the stale function declarations from the header file. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-9-imre.deak@intel.com
2026-01-13drm/i915/dp: Drop intel_dp parameter from ↵Imre Deak
intel_dp_compute_config_link_bpp_limits() The intel_dp pointer can be deducted from the connector pointer, so it's enough to pass only connector to intel_dp_compute_config_link_bpp_limits(), do so. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-8-imre.deak@intel.com
2026-01-13drm/i915/dp: Align min/max compressed BPPs when calculating BPP limitsImre Deak
Align the minimum/maximum DSC compressed BPPs to the corresponding source compressed BPP limits already when computing the BPP limits. This alignment is also performed later during state computation, however there is no reason to initialize the limits to an unaligned/incorrect value. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-7-imre.deak@intel.com
2026-01-13drm/i915/dp: Align min/max DSC input BPPs to sink capsImre Deak
Align the minimum/maximum DSC input BPPs to the corresponding sink DSC input BPP capability limits already when computing the BPP limits. This alignment is also performed later during state computation, however there is no reason to initialize the limits to an unaligned/incorrect value. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-6-imre.deak@intel.com
2026-01-13drm/i915/dp: Factor out align_max_vesa_compressed_bpp_x16()Imre Deak
Factor out align_max_vesa_compressed_bpp_x16(), also used later for computing the maximum DSC compressed BPP limit. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-5-imre.deak@intel.com
2026-01-13drm/i915/dp: Factor out align_max_sink_dsc_input_bpp()Imre Deak
Factor out align_max_sink_dsc_input_bpp(), also used later for computing the maximum DSC input BPP limit. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-4-imre.deak@intel.com
2026-01-13drm/i915/dp: Drop unused timeslots param from dsc_compute_link_config()Imre Deak
Drop the unused timeslots parameter from dsc_compute_link_config() and other functions calling it. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251222153547.713360-2-imre.deak@intel.com
2026-01-09drm/i915/cdclk: Incorporate Xe3_LPD changes for CD2X dividerGustavo Sousa
On Xe3_LPD, there is no instruction to program the CD2X divider anymore and the hardware is expected to always use the default value of 0b00, meaning "divide by 1". With that, the CDCLK_CTL register was changed so that: (1) The field "CD2X Divider Select" became a debug-only field. Because we are programming CDCLK_CTL with a direct write instead of read-modify-write operation, we still need to program "CD2X Divider Select" in order to keep the field from deviating from its default value. Let's, however, throw a warning if we encounter a CDCLK value that would result in an unexpected value for that field. (2) The field "CD2X Pipe Select" has been removed. In fact, some debugging in a PTL machine showed that such field comes back as zero after writing a non-zero value to it. As such, do not program it starting with Xe3_LPD. v2: - Add missing "val |= " when calling bxt_cdclk_cd2x_pipe(). (Dnyaneshwar) Bspec: 68864, 69090 Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Link: https://patch.msgid.link/20260106-xe3_lpd-no-cd2x-divider-v2-1-06e5cbc9dabb@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-01-09Merge tag 'drm-misc-next-2026-01-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.20: UAPI Changes: Cross-subsystem Changes: Core Changes: - draw: Add API to check if a format conversion can be done - panic: Rename draw_panic_static_* to draw_panic_screen_*, Add kunit tests - shmem: Improve tests Driver Changes: - ast: Big endian fixes - etnaviv: Add PPU flop reset support - panfrost: Add GPU_PM_RT support for RZ/G3E SoC - panthor: multiple fixes around VM termination, huge page support - pl111: Fix build regression - v3d: Fix DMA segment size - bridge: - Add connector argument to .hpd_notify - Plenty of patches to convert existing drivers to refcounting - Convert Rockchip's inno hdmi support to a proper bridge - lontium-lt9611uxc: Switch to HDMI audio helpers - panel: - New panel: BOE NV140WUM-T08 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <mripard@redhat.com> Link: https://patch.msgid.link/20260108-literate-nyala-of-courtesy-de501a@houat
2026-01-07drm/i915/lt_phy_regs: Fix the SPDX identifier commentAnkit Nautiyal
Fix the SPDX identifier comment as per the licensing rules [1]. [1] https://www.kernel.org/doc/html/latest/process/license-rules.html Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105113544.574323-10-ankit.k.nautiyal@intel.com
2026-01-07drm/i915/intel_lt_phy: Fix the SPDX identifier commentAnkit Nautiyal
Fix the SPDX identifier comment as per the licensing rules [1]. [1] https://www.kernel.org/doc/html/latest/process/license-rules.html v2: Drop the superfluous blank line. (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105121929.576304-1-ankit.k.nautiyal@intel.com
2026-01-07drm/i915/intel_gvt_api: Fix the SPDX identifier commentAnkit Nautiyal
Fix the SPDX identifier comment as per the licensing rules [1]. [1] https://www.kernel.org/doc/html/latest/process/license-rules.html Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105113544.574323-8-ankit.k.nautiyal@intel.com
2026-01-07drm/i915/intel_dsb_buffer: Fix the SPDX identifier commentAnkit Nautiyal
Fix the SPDX identifier comment as per the licensing rules [1]. [1] https://www.kernel.org/doc/html/latest/process/license-rules.html Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105113544.574323-7-ankit.k.nautiyal@intel.com
2026-01-07drm/i915/intel_dsb: Fix the SPDX identifier commentAnkit Nautiyal
Fix the SPDX identifier comment as per the licensing rules [1]. [1] https://www.kernel.org/doc/html/latest/process/license-rules.html Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105113544.574323-6-ankit.k.nautiyal@intel.com
2026-01-07drm/i915/intel_display_params: Fix the SPDX identifier commentAnkit Nautiyal
Fix the SPDX identifier comment as per the licensing rules [1]. [1] https://www.kernel.org/doc/html/latest/process/license-rules.html Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105113544.574323-5-ankit.k.nautiyal@intel.com
2026-01-07drm/i915/intel_cx0_phy_regs: Fix the SPDX identifier commentAnkit Nautiyal
Fix the SPDX identifier comment as per the licensing rules [1]. [1] https://www.kernel.org/doc/html/latest/process/license-rules.html Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105113544.574323-4-ankit.k.nautiyal@intel.com
2026-01-07drm/i915/intel_cx0_phy: Fix the SPDX identifier commentAnkit Nautiyal
Fix the SPDX identifier comment as per the licensing rules [1]. [1] https://www.kernel.org/doc/html/latest/process/license-rules.html Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105113544.574323-3-ankit.k.nautiyal@intel.com
2026-01-07drm/i915/intel_alpm: Fix the SPDX identifier commentAnkit Nautiyal
Fix the SPDX identifier comment as per the licensing rules [1]. [1] https://www.kernel.org/doc/html/latest/process/license-rules.html Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105113544.574323-2-ankit.k.nautiyal@intel.com
2026-01-05drm/i915/cdclk: Implement Wa_13012396614Gustavo Sousa
A new workaround was defined for Xe3_LPD, which requires a tweak on how we handle MDCLK selection. Implement it. Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Link: https://patch.msgid.link/20251222-display-wa-13012396614-timing-of-mdclk-source-selection-v1-2-a2f7e9447f7a@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-01-05drm/i915/display_wa: Keep enum intel_display_wa sortedGustavo Sousa
For a consistent way of updating enum intel_display_wa, let's sort it by lineage number and add a comment asking for future updates to keep it sorted. In the same way, let's also keep __intel_display_wa() sorted. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251222-display-wa-13012396614-timing-of-mdclk-source-selection-v1-1-a2f7e9447f7a@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-01-05drm/i915/ltphy: Provide protection against unsupported modesSuraj Kandpal
We need to make sure we return some port clock in case we have unsupported LT PHY modes or if we were not able to read the LT PHY state for whatever reason and the mode ends up being 0. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105055937.136522-3-suraj.kandpal@intel.com
2026-01-05drm/i915/ltphy: Compare only certain fields in state verify functionSuraj Kandpal
Verify only the config[0,2] fields in the LT PHY state since these are the only reliable values we can get back when we read the VDR registers. The reason being that the state does not persist for other VDR registers when power gating comes into picture. Though not ideal this change does not hit us badly in perspective of how we use the compare function to decide if fastset is required or if we wrote the state correctly. VDR0_CONFIG and VDR1_CONFIG hold the values that indicate the PLL operating mode and link rate which is usually what we need to check if something has changed or not. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105055937.136522-2-suraj.kandpal@intel.com
2026-01-05drm/i915/ltphy: Remove state verification for LT PHY fieldsSuraj Kandpal
Currently we do state verification for all VDR Registers. Remove LT PHY State verification for all VDR register fields other than VDR0_CONFIG and VDR2_CONFIG. The reason being that VDR0_CONFIG and VDR2_CONFIG are the only reliable shadow register which hold onto their values over the course of power gatings which happen internally due to features like PSR/PR. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105055937.136522-1-suraj.kandpal@intel.com
2026-01-02drm/i915/display: remove accidentally added empty fileJani Nikula
intel_display_limits.c was never supposed to be added. Remove it. Fixes: f3255cf4490e ("drm/i915/display: Add APIs to be used by gvt to get the register offsets") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251231103232.627666-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-30drm/i915/utils: drop unnecessary ifdefsJani Nikula
The i915_utils.h and intel_display_utils.h were in some cases included from the same files, the former via i915_drv.h and the latter directly. This lead to a clash between MISSING_CASE() and fetch_and_zero() defined in both, requiring ifdefs. With the display dependency on i915_drv.h removed, we can also remove the now unnecessary ifdefs. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/f40a1fd365cbcfb77bd76ce0041c4523699f6052.1767009044.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-30drm/i915: drop i915 param from i915_fence{, _context}_timeout()Jani Nikula
The i915_fence_context_timeout() and i915_fence_timeout() functions both have the struct drm_i915_private parameter, which is unused. It's likely in preparation for something that just didn't end up happening. Remove them, dropping the last struct drm_i915_private usage for xe display build. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/dce86cb031d523a95a96ed2bf9c93bb28e6b20ab.1767009044.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-30drm/i915/vrr: Enable DC BalanceMitul Golani
Enable DC Balance from vrr compute config and related hw flag. Also to add pipe restrictions along with this. --v2: - Use dc balance check instead of source restriction. --v3: - Club pipe restriction check with dc balance enablement. (Ankit) --v4: - Separate out Pipe restrictions to patch#7 Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-19-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/display: Add function to configure event for dc balanceMitul Golani
Configure pipe dmc event for dc balance enable/disable. --v2: - Keeping function and removing unnecessary comments. (Jani, Nikula) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-18-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Pause DC Balancing for DSB commitsVille Syrjälä
Pause the DMC DC Balancing for the remainder of the commit so that vmin/vmax won't change after we've baked them into the DSB vblank evasion commands. --v2: - Remove typo. (Ankit) - Separate vrr enable structuring. (Ankit) --v3: - Add gaurd before accessing DC balance bits. - Remove redundancy checks. --v4: - Move events to separate function. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-17-mitulkumar.ajitkumar.golani@intel.com
generated by cgit v1.2.3 (git 2.25.1) at 2026-08-09 16:40:57 +0000