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path: root/drivers/gpu/drm/i915/display/intel_cx0_phy.c
AgeCommit message (Expand)Author
2025-12-24drm/i915/cx0: Use the consolidated HDMI tablesSuraj Kandpal
2025-12-19drm/i915/cx0: Toggle powerdown states for C10 on HDMIGustavo Sousa
2025-12-19drm/i915/cx0: Use a more accurate message for powerdown change failureGustavo Sousa
2025-12-10drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug messageImre Deak
2025-12-01drm/i915/power: convert intel_wakeref_t to struct ref_tracker *Jani Nikula
2025-11-21drm/i915/cx0: Read out power-down state of both PHY lanes for reversed lanesImre Deak
2025-11-21drm/i915/cx0: Read out power-down state of both TXs in PHY lane 0Imre Deak
2025-11-19drm/i915/cx0: Enable dpll framework for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Add MTL+ Thunderbolt PLL hooksImre Deak
2025-11-19drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDIMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .dump_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak
2025-11-19drm/i915/cx0: Factor out C10 msgbus access start/end helpersImre Deak
2025-11-11drm/i915/de: Use intel_de_wait_for_{set,clear}_ms()Ville Syrjälä
2025-11-11drm/i915/de: Use intel_de_wait_for_{set,clear}_us()Ville Syrjälä
2025-11-11drm/i915/de: Use intel_de_wait_ms() for the obvious casesVille Syrjälä
2025-11-11drm/i915/de: Use intel_de_wait_us()Ville Syrjälä
2025-11-11drm/i915/de: Include units in intel_de_wait*() function namesVille Syrjälä
2025-11-07drm/i915/cx0: s/XELPDP_PORT_RESET_END_TIMEOUT/XELPDP_PORT_RESET_END_TIMEOUT_MS/Ville Syrjälä
2025-11-07drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/Ville Syrjälä
2025-11-07drm/i915/cx0: Get rid of XELPDP_MSGBUS_TIMEOUT_FAST_USVille Syrjälä
2025-11-07drm/i915/cx0: Replace XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US with XELPDP_POR...Ville Syrjälä
2025-11-07drm/i915/cx0: Nuke extraneous timeout debugsVille Syrjälä
2025-11-01drm/i915/ltphy: Define LT PHY PLL state verify functionSuraj Kandpal
2025-11-01drm/i915/ltphy: Hook up LT Phy Enable & Disable sequencesSuraj Kandpal
2025-11-01drm/i915/ltphy: Program the rest of the LT Phy Enable sequenceSuraj Kandpal
2025-11-01drm/i915/ltphy: Program the P2P Transaction flow for LT PhySuraj Kandpal
2025-11-01drm/i915/ltphy: Program the VDR PLL registers for LT PHYSuraj Kandpal
2025-11-01drm/i915/ltphy: Read PHY_VDR_0_CONFIG registerSuraj Kandpal
2025-11-01drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequenceSuraj Kandpal
2025-11-01drm/i915/cx0: Move the HDMI FRL function to intel_hdmiSuraj Kandpal
2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal
2025-11-01drm/i915/cx0: Change register bit naming for powerdown valuesSuraj Kandpal
2025-10-31drm/i915/display: switch to intel_display_utils.hJani Nikula
2025-10-16drm/i915/display: Add missing clock to C10 PHY state compute/HW readoutImre Deak
2025-10-16drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programmingImre Deak
2025-10-16drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programmingImre Deak
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