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path: root/drivers/gpu/drm/i915/display/intel_color.c
AgeCommit message (Expand)Author
2025-12-04drm/i915/color: Add 3D LUT to color pipelineChaitanya Kumar Borah
2025-12-04drm/i915/color: Program Plane Post CSC RegistersUma Shankar
2025-12-04drm/i915/color: Program Pre-CSC registersUma Shankar
2025-12-04drm/i915/color: Add framework to program PRE/POST CSC LUTUma Shankar
2025-12-04drm/i915/color: Add plane CTM callback for D12 and beyondUma Shankar
2025-12-04drm/i915/color: Preserve sign bit when int_bits is ZeroChaitanya Kumar Borah
2025-12-04drm/i915/color: Add framework to program CSCChaitanya Kumar Borah
2025-11-06drm/i915/xe3p_lpd: Remove gamma,csc bottom color checksSai Teja Pottumuttu
2025-10-31drm/i915/display: switch to intel_display_utils.hJani Nikula
2025-09-25drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblankAnkit Nautiyal
2025-05-26drm/i915/color: Do not pre-load LUTs with DB registersChaitanya Kumar Borah
2025-05-26drm/i915/display: use GOSUB to program double buffered LUT registersChaitanya Kumar Borah
2025-05-26drm/i915: s/dsb_color_vblank/dsb_colorChaitanya Kumar Borah
2025-04-01drm/i915: reduce intel_wakeref.h dependenciesJani Nikula
2025-03-21drm/i915/color: prefer display->platform.<platform> checksJani Nikula
2025-02-12drm/i915/vrr: Check that the push send bit is clear after delayed vblankVille Syrjälä
2025-02-12drm/i915/vrr: Reorder the DSB "wait for safe window" vs. TRANS_PUSHVille Syrjälä
2025-02-12drm/i915/dsb: Compute use_dsb earlierVille Syrjälä
2025-01-23drm/i915/display: fix typos in i915/display filesNitin Gote
2024-12-16drm/i915/uncore: add to_intel_uncore() and use itJani Nikula
2024-11-28drm/i915/color: Stop using non-posted DSB writes for legacy LUTVille Syrjälä
2024-11-28drm/i915/dsb: Don't use indexed register writes needlesslyVille Syrjälä
2024-10-29drm/i915/color: Make color .get_config() mandatoryVille Syrjälä
2024-10-29drm/i915/color: Convert color management code to intel_displayVille Syrjälä
2024-10-29drm/i915/color: Pimp debugsVille Syrjälä
2024-10-04drm/i915/dsb: Use DSB for plane/color management updatesVille Syrjälä
2024-10-04drm/i915: Plumb 'dsb' all way to the color commit hooksVille Syrjälä
2024-10-04drm/i915: Plumb 'dsb' all way to the plane hooksVille Syrjälä
2024-09-19drm/i915/color: Extract intel_color_modeset()Ville Syrjälä
2024-08-29drm/i915/dsb: Use chained DSBs for LUT programmingVille Syrjälä
2024-08-29drm/i915/dsb: s/dsb/dsb_color_vblank/Ville Syrjälä
2024-06-20drm/i915/dsb: Plumb the whole atomic state into intel_dsb_prepare()Ville Syrjälä
2024-06-20drm/i915: Pass the whole atomic state to intel_color_prepare_commit()Ville Syrjälä
2024-06-05drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare()Ville Syrjälä
2024-05-27drm/i915: Bury c8_planes_changed() in intel_color_check()Ville Syrjälä
2024-05-27drm/i915: Hide the intel_crtc_needs_color_update() inside intel_color_check()Ville Syrjälä
2024-05-27drm/i915: Plumb the entire atomic state into intel_color_check()Ville Syrjälä
2024-05-24drm/i915: pass dev_priv explicitly to PIPEGCMAXJani Nikula
2024-05-24drm/i915: pass dev_priv explicitly to DSPCNTRJani Nikula
2024-05-22drm/i915: Extract i9xx_plane_regs.hVille Syrjälä
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C22Jani Nikula
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C21_C20Jani Nikula
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C12Jani Nikula
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C11_C10Jani Nikula
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C02Jani Nikula
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C01_C00Jani Nikula
2024-04-30drm/i915: pass dev_priv explicitly to PALETTEJani Nikula
2024-02-09drm/i915/color: Use per-device debugsVille Syrjälä
2023-11-23drm/i915: Fix glk+ degamma LUT conversionsVille Syrjälä
2023-11-23drm/i915: s/clamp()/min()/ in i965_lut_11p6_max_pack()Ville Syrjälä
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