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path: root/drivers/clk
AgeCommit message (Expand)Author
2021-09-30clk: imx: Rework all imx_clk_hw_composite wrappersAbel Vesa
2021-09-30clk: imx: Rework all clk_hw_register_divider wrappersAbel Vesa
2021-09-30clk: imx: Rework all clk_hw_register_mux wrappersAbel Vesa
2021-09-30clk: imx: Rework all clk_hw_register_gate2 wrappersAbel Vesa
2021-09-28Merge tag 'renesas-clk-for-v5.15-tag3' of git://git.kernel.org/pub/scm/linux/...Stephen Boyd
2021-09-28clk: renesas: r8a779a0: Add Z0 and Z1 clock supportGeert Uytterhoeven
2021-09-24clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen
2021-09-24clk: renesas: rzg2l: Fix clk status functionBiju Das
2021-09-24clk: renesas: r9a07g044: Add GbEthernet clock/resetBiju Das
2021-09-24clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK criticalBiju Das
2021-09-24clk: renesas: rzg2l: Add support to handle coupled clocksBiju Das
2021-09-24clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das
2021-09-24clk: renesas: rzg2l: Add support to handle MUX clocksBiju Das
2021-09-24clk: renesas: r8a779a0: Add TPU clockWolfram Sang
2021-09-23clk: meson: meson8b: Make the video clock trees mutableMartin Blumenstingl
2021-09-23clk: meson: meson8b: Initialize the HDMI PLL registersMartin Blumenstingl
2021-09-23clk: meson: meson8b: Add the HDMI PLL M/N parametersMartin Blumenstingl
2021-09-23clk: meson: meson8b: Add the vid_pll_lvds_en gate clockMartin Blumenstingl
2021-09-23clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_selMartin Blumenstingl
2021-09-23clk: meson: meson8b: Export the video clocksMartin Blumenstingl
2021-09-21clk: rockchip: use module_platform_driver_probeMiles Chen
2021-09-20clk: rockchip: rk3399: expose PCLK_COREDBG_{B,L}Brian Norris
2021-09-20clk: rockchip: rk3399: make CPU clocks criticalBrian Norris
2021-09-17clk: imx: Rework all clk_hw_register_gate wrappersAbel Vesa
2021-09-17clk: imx: Make mux/mux2 clk based helpers use clk_hw based onesAbel Vesa
2021-09-17clk: imx: Remove unused helpersAbel Vesa
2021-09-14clk: mediatek: Export clk_ops structures to modulesStephen Boyd
2021-09-14clk: mvebu: ap-cpu-clk: Fix a memory leak in error handling pathsChristophe JAILLET
2021-09-14clk: mediatek: support COMMON_CLK_MT6779 module buildMiles Chen
2021-09-14clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen
2021-09-14clk: composite: export clk_register_compositeMiles Chen
2021-09-14clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for regis...Rob Herring
2021-09-14clk: mediatek: Add MT8195 apusys clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 imp i2c wrapper clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 wpesys clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 vppsys1 clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 vppsys0 clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 vencsys clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 vdosys1 clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 vdosys0 clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 vdecsys clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 scp adsp clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 mfgcfg clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 ipesys clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 imgsys clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 ccusys clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 camsys clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 infrastructure clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 peripheral clock supportChun-Jie Chen
2021-09-14clk: mediatek: Add MT8195 topckgen clock supportChun-Jie Chen