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path: root/drivers/clk/mediatek/clk-pll.h
AgeCommit message (Expand)Author
2026-01-22clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocksNicolas Frattaroli
2026-01-22clk: mediatek: Pass device to clk_hw_register for PLLsNicolas Frattaroli
2026-01-22clk: mediatek: Refactor pll registration to pass deviceNicolas Frattaroli
2025-10-06Merge branch 'clk-determine-rate' into clk-nextStephen Boyd
2025-09-21clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENCLaura Nao
2025-09-21clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable controlLaura Nao
2025-09-08clk: mediatek: pll: convert from round_rate() to determine_rate()Brian Masney
2024-01-03clk: mediatek: add pcw_chg_bit control for PLLs of MT7988Sam Shih
2022-11-29clk: mediatek: Export PLL operations symbolsJohnson Wang
2022-05-19clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai
2022-02-17clk: mediatek: pll: Implement error handling in register APIChen-Yu Tsai
2022-02-17clk: mediatek: pll: Implement unregister APIChen-Yu Tsai
2022-02-17clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai
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