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path: root/arch/x86/kernel/cpu
AgeCommit message (Expand)Author
2018-05-17x86/speculation, KVM: Implement support for VIRT_SPEC_CTRL/LS_CFGThomas Gleixner
2018-05-17x86/bugs: Rework spec_ctrl base and mask logicThomas Gleixner
2018-05-17x86/bugs: Remove x86_spec_ctrl_set()Thomas Gleixner
2018-05-17x86/bugs: Expose x86_spec_ctrl_base directlyThomas Gleixner
2018-05-17x86/bugs: Unify x86_spec_ctrl_{set_guest,restore_host}Borislav Petkov
2018-05-17x86/speculation: Rework speculative_store_bypass_update()Thomas Gleixner
2018-05-17x86/speculation: Add virtualized speculative store bypass disable supportTom Lendacky
2018-05-17x86/bugs, KVM: Extend speculation control for VIRT_SPEC_CTRLThomas Gleixner
2018-05-17x86/cpufeatures: Add FEATURE_ZENThomas Gleixner
2018-05-17x86/cpufeatures: Disentangle SSBD enumerationThomas Gleixner
2018-05-17x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration from IBRSThomas Gleixner
2018-05-17x86/speculation: Use synthetic bits for IBRS/IBPB/STIBPBorislav Petkov
2018-05-16x86/mtrr: Convert to use strncpy_from_user() helperAndy Shevchenko
2018-05-16x86/mtrr: Convert to use match_string() helperAndy Shevchenko
2018-05-13x86/mtrr: Rename main.c to mtrr.c and remove duplicate prefixesJoe Perches
2018-05-13x86/CPU: Move x86_cpuinfo::x86_max_cores assignment to detect_num_cpu_cores()Thomas Gleixner
2018-05-13x86/Centaur: Report correct CPU/cache topologyDavid Wang
2018-05-13x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo()David Wang
2018-05-13x86/CPU: Make intel_num_cpu_cores() genericDavid Wang
2018-05-13x86/CPU: Move cpu local function declarations to local headerThomas Gleixner
2018-05-12x86/bugs: Fix the parameters alignment and missing voidKonrad Rzeszutek Wilk
2018-05-10x86/bugs: Make cpu_show_common() staticJiri Kosina
2018-05-10x86/bugs: Fix __ssb_select_mitigation() return typeJiri Kosina
2018-05-09x86/bugs: Rename _RDS to _SSBDKonrad Rzeszutek Wilk
2018-05-06x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when availableSuravee Suthikulpanit
2018-05-06x86/CPU: Modify detect_extended_topology() to return resultSuravee Suthikulpanit
2018-05-06x86/CPU/AMD: Calculate last level cache ID from number of sharing threadsSuravee Suthikulpanit
2018-05-06x86/CPU: Rename intel_cacheinfo.c to cacheinfo.cBorislav Petkov
2018-05-06x86/CPU/AMD: Have smp_num_siblings and cpu_llc_id always be presentBorislav Petkov
2018-05-06x86/MCE: Fix stack out-of-bounds write in mce-inject.c: Flags_read()Luck, Tony
2018-05-06x86/MCE: Enable MCE broadcasting on new Centaur CPUsDavid Wang
2018-05-05x86/speculation: Make "seccomp" the default mode for Speculative Store BypassKees Cook
2018-05-05seccomp: Move speculation migitation control to arch codeThomas Gleixner
2018-05-05prctl: Add force disable speculationThomas Gleixner
2018-05-05x86/bugs: Make boot modes __ro_after_initKees Cook
2018-05-03nospec: Allow getting/setting on non-current taskKees Cook
2018-05-03x86/speculation: Add prctl for Speculative Store Bypass mitigationThomas Gleixner
2018-05-03x86/process: Allow runtime control of Speculative Store BypassThomas Gleixner
2018-05-03x86/speculation: Create spec-ctrl.h to avoid include hellThomas Gleixner
2018-05-03x86/bugs/AMD: Add support to disable RDS on Fam[15,16,17]h if requestedKonrad Rzeszutek Wilk
2018-05-03x86/bugs: Whitelist allowed SPEC_CTRL MSR valuesKonrad Rzeszutek Wilk
2018-05-03x86/bugs/intel: Set proper CPU features and setup RDSKonrad Rzeszutek Wilk
2018-05-03x86/bugs: Provide boot parameters for the spec_store_bypass_disable mitigationKonrad Rzeszutek Wilk
2018-05-03x86/bugs: Expose /sys/../spec_store_bypassKonrad Rzeszutek Wilk
2018-05-03x86/bugs, KVM: Support the combination of guest and host IBRSKonrad Rzeszutek Wilk
2018-05-03x86/bugs: Read SPEC_CTRL MSR during boot and re-use reserved bitsKonrad Rzeszutek Wilk
2018-05-03x86/bugs: Concentrate bug reporting into a separate functionKonrad Rzeszutek Wilk
2018-05-03x86/bugs: Concentrate bug detection into a separate functionKonrad Rzeszutek Wilk
2018-05-02x86/cpu: Restore CPUID_8000_0008_EBX reloadThomas Gleixner
2018-04-26x86/cpu/intel: Add missing TLB cpuid valuesjacek.tomaka@poczta.fm
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