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authorMatt Ranostay <mranostay@ti.com>2024-05-07 15:25:45 +0530
committerVignesh Raghavendra <vigneshr@ti.com>2024-06-12 21:31:27 +0530
commitbed97e94ee2d422f54334bd509b50ae2a3577f67 (patch)
treeda98eb14ca01a74a4bfed1863e246cda97ce0338
parent75843b63741b122711d07b8fd672485e69223419 (diff)
arm64: dts: ti: k3-j784s4-evm: Enable USB3 support
The board uses SERDES0 Lane 3 for USB3 IP. So update the SerDes lane info for USB. Add the pin mux data and enable USB3 support. Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Tested-by: Andrew Halaney <ahalaney@redhat.com> # k3-j784s4-evm Link: https://lore.kernel.org/r/20240507095545.8210-3-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
-rw-r--r--arch/arm64/boot/dts/ti/k3-j784s4-evm.dts41
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 500b70ffe0db..a29d302b16b7 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -415,6 +415,13 @@
J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-default-pins {
+ bootph-all;
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
};
&wkup_pmx2 {
@@ -1171,6 +1178,40 @@
<&k3_clks 218 22>;
};
+&serdes0 {
+ status = "okay";
+
+ serdes0_usb_link: phy@3 {
+ reg = <3>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 4>;
+ };
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&usb_serdes_mux {
+ idle-states = <0>; /* USB0 to SERDES lane 3 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
&serdes_wiz4 {
status = "okay";
};