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authorPing-Ke Shih <pkshih@realtek.com>2025-08-26 16:53:32 +0800
committerPing-Ke Shih <pkshih@realtek.com>2025-09-01 10:54:41 +0800
commit110f3c11f440d78ef8a181f75456e24e428f69e4 (patch)
tree996cf5686b6c1268f265919b83acd90267161b05
parent83d823ab27da7030d25001b7e293059112ee7734 (diff)
wifi: rtw89: pci: add RPP parser v1
The new format contains more information including TX DMA channel, actual TX link and etc. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20250826085332.28463-1-pkshih@realtek.com
-rw-r--r--drivers/net/wireless/realtek/rtw89/pci.c12
-rw-r--r--drivers/net/wireless/realtek/rtw89/pci.h15
2 files changed, 27 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c
index cc54694859a6..1316671cb31b 100644
--- a/drivers/net/wireless/realtek/rtw89/pci.c
+++ b/drivers/net/wireless/realtek/rtw89/pci.c
@@ -580,6 +580,18 @@ void rtw89_pci_parse_rpp(struct rtw89_dev *rtwdev, void *_rpp,
}
EXPORT_SYMBOL(rtw89_pci_parse_rpp);
+void rtw89_pci_parse_rpp_v1(struct rtw89_dev *rtwdev, void *_rpp,
+ struct rtw89_pci_rpp_info *rpp_info)
+{
+ const struct rtw89_pci_rpp_fmt_v1 *rpp = _rpp;
+
+ rpp_info->seq = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_PCIE_SEQ_V1_MASK);
+ rpp_info->qsel = le32_get_bits(rpp->w1, RTW89_PCI_RPP_W1_QSEL_V1_MASK);
+ rpp_info->tx_status = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_TX_STATUS_V1_MASK);
+ rpp_info->txch = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_DMA_CH_MASK);
+}
+EXPORT_SYMBOL(rtw89_pci_parse_rpp_v1);
+
static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, void *rpp)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index b0c6f4d38bf5..fc8268eb44db 100644
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -1498,6 +1498,19 @@ struct rtw89_pci_rpp_fmt {
__le32 dword;
} __packed;
+#define RTW89_PCI_RPP_W0_MACID_V1_MASK GENMASK(9, 0)
+#define RTW89_PCI_RPP_W0_DMA_CH_MASK GENMASK(13, 10)
+#define RTW89_PCI_RPP_W0_TX_STATUS_V1_MASK GENMASK(16, 14)
+#define RTW89_PCI_RPP_W0_PCIE_SEQ_V1_MASK GENMASK(31, 17)
+#define RTW89_PCI_RPP_W1_QSEL_V1_MASK GENMASK(5, 0)
+#define RTW89_PCI_RPP_W1_TID_IND BIT(6)
+#define RTW89_PCI_RPP_W1_CHANGE_LINK BIT(7)
+
+struct rtw89_pci_rpp_fmt_v1 {
+ __le32 w0;
+ __le32 w1;
+} __packed;
+
struct rtw89_pci_rx_bd_32 {
__le16 buf_size;
__le16 opt;
@@ -1736,6 +1749,8 @@ u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
dma_addr_t dma, u8 *add_info_nr);
void rtw89_pci_parse_rpp(struct rtw89_dev *rtwdev, void *_rpp,
struct rtw89_pci_rpp_info *rpp_info);
+void rtw89_pci_parse_rpp_v1(struct rtw89_dev *rtwdev, void *_rpp,
+ struct rtw89_pci_rpp_info *rpp_info);
void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable);
void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);