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2026-02-24bootm: fix booting kernel_noload imageCHECK/check-bootm-fit-noloadLudwig Nussel
FIT images don't work without having to explicitly specify physical load addresses. Digging into that it looks like a flaw in bootm_load_os(). It duplicates images->os for convenience. However, the code handling "kernel_noload" images then updates the load address in the copy with the value lmb_alloc_mem() returned. Later there's another call to lmb_alloc_mem() that uses the old value. This leads to havoc due to subsequent calls of lmb_alloc_mem() picking too low addresses. The "fix" is to mark the local variable const to avoid accidental assignments. This works but IMO the logic is still flawed somehow as this leads to overlapping lmb reservations. I guess the fixed reservation should only be done when the noload path wasn't hit. Without the change: + bootm 0x40200000#qemu-arm 0x40200000#qemu-arm 0x40000000 Using 'qemu-arm' configuration Verifying Hash Integrity ... OK Trying 'kernel' kernel subimage Description: Linux kernel Created: 2026-02-24 14:10:09 UTC Type: Kernel Image (no loading done) Compression: gzip compressed Data Start: 0x402000b8 Data Size: 12227440 Bytes = 11.7 MiB Hash algo: sha256 Hash value: 7ea661fdecdd1127edd419cfbf8bff52e2d5ac55c... Verifying Hash Integrity ... sha256+ OK Using 'qemu-arm' configuration Verifying Hash Integrity ... OK Trying 'ramdisk' ramdisk subimage Description: Initial ramdisk Created: 2026-02-24 14:10:09 UTC Type: RAMDisk Image Compression: uncompressed Data Start: 0x40da9528 Data Size: 1067114 Bytes = 1 MiB Architecture: AArch64 OS: Linux Load Address: unavailable Entry Point: unavailable Hash algo: sha256 Hash value: 2a711dcb5f58615187645ccec615c67eddcfbb3138... Verifying Hash Integrity ... sha256+ OK Booting using the fdt blob at 0x40000000 Working FDT set to 40000000 Uncompressing Kernel Image (no loading done) to 13a400000 Loading Ramdisk to 400fb000, end 401ff86a ... OK device tree - allocation error FDT creation failed! resetting ... Bloblist at 0 not found (err=-2) alloc space exhausted ptr 400 limit 0 Bloblist at 0 not found (err=-2) [reset] After: + bootm 0x40200000#qemu-arm 0x40200000#qemu-arm 0x40000000 Using 'qemu-arm' configuration Verifying Hash Integrity ... OK Trying 'kernel' kernel subimage Description: Linux kernel Created: 2026-02-24 14:10:09 UTC Type: Kernel Image (no loading done) Compression: gzip compressed Data Start: 0x402000b8 Data Size: 12227440 Bytes = 11.7 MiB Hash algo: sha256 Hash value: 7ea661fdecdd1127edd419cfbf8bff52e2d5ac55ce... Verifying Hash Integrity ... sha256+ OK Using 'qemu-arm' configuration Verifying Hash Integrity ... OK Trying 'ramdisk' ramdisk subimage Description: Initial ramdisk Created: 2026-02-24 14:10:09 UTC Type: RAMDisk Image Compression: uncompressed Data Start: 0x40da9528 Data Size: 1067114 Bytes = 1 MiB Architecture: AArch64 OS: Linux Load Address: unavailable Entry Point: unavailable Hash algo: sha256 Hash value: 2a711dcb5f58615187645ccec615c67eddcfbb3138... Verifying Hash Integrity ... sha256+ OK Booting using the fdt blob at 0x40000000 Working FDT set to 40000000 Uncompressing Kernel Image (no loading done) to 13a400000 Loading Ramdisk to 13a2fb000, end 13a3ff86a ... OK Loading Device Tree to 000000013a1f8000, end 000000013a2fafff ... OK Working FDT set to 13a1f8000 Starting kernel ... Signed-off-by: Ludwig Nussel <ludwig.nussel@siemens.com>
2026-02-23board: Correct usage of fdtfile=CONFIG_DEFAULT_FDT_FILETom Rini
As explained in commit 03d2d5fc003f ("board: sifive: unmatched: set fdtfile with unquoted variable.") using the syntax of 'fdtfile=CONFIG_DEFAULT_FDT_FILE' in the plain text environment files will lead to extraneous and problematic "s in the output. This is fixed by using fdtfile=DEFAULT_FDT_FILE which was introduced recently. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-23Merge patch series "net: mdio-mt7531-mmio: consolidate and improve probe"Tom Rini
Christian Marangi <ansuelsmth@gmail.com> says: This small series consolidate header usage of mdio-mt7531-mmio driver and improve usage in preparation for support of OF PHY autoprobe. This driver is still not used (as it will be used by AN7581/AN7583) in the OF mode (it's used by MT7988 for the MDIO functions) For OF PHY to be correctly autoprobed, the MDIO driver needs to attached to the MDIO node (the parent of the PHY nodes) With such change the MDIO driver can be binded with the MDIO node instead of the switch node as previously required. Link: https://lore.kernel.org/r/20260209114515.1916-1-ansuelsmth@gmail.com
2026-02-23net: mdio-mt7531-mmio: improve parsing of switch register on probeChristian Marangi
The MDIO node is ALWAYS a parent of the MT7531 switch node and the MDIO registers are in the MT7531 register space (in the context of MT7988 it's all memory-mapped) With these assumption, we can simplify and permit better usage of PHY OF automatic probing by binding the mt7531-mdio-mmio driver with the MDIO node instead of the switch node. For OF PHY to be correctly autoprobed, the MDIO driver needs to attached to the MDIO node (the parent of the PHY nodes). The driver will reach the parent node (the switch node) and will parse the register address from there. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2026-02-23net: mdio-mt7531-mmio: use common header priv structChristian Marangi
Instead of having duplicate priv struct for mdio-mt7531-mmio driver in both driver and header, use the one exposed by the header directly. This make sure we have consistent priv struct if the driver will be updated in the future. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2026-02-23Merge patch series "am62dxx-evm: Add SPI flash support"Tom Rini
Paresh Bhagat <p-bhagat@ti.com> says: This series enables SPI flash support for the AM62DX EVM platform. The first patch enables the required SPI flash configuration options in both A53 and R5 defconfigs, including Cadence QSPI driver support, SFDP support, and Spansion S28HX-T flash compatibility. The second patch adds the necessary device tree configuration for the R5 SPL to support OSPI flash access during the boot process. Boot logs https://gist.github.com/paresh-bhagat12/ca9a05aa443c71e8baf6d8506f6ccc22 Link: https://lore.kernel.org/r/20260209072820.2576854-1-p-bhagat@ti.com
2026-02-23configs: am62dx_evm: Enable SPI flash supportParesh Bhagat
Enable SPI flash support for AM62DX EVM by adding Cadence QSPI driver, configuring 25MHz speed, and enabling SFDP support with Spansion S28HX-T flash compatibility. Enable required SPI and MTD configs for both A53 and R5 configurations to allow booting from SPI flash. Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
2026-02-23arm: dts: k3-am62d2-r5: Add DMA and OSPI configurationParesh Bhagat
Enable WKUP UART0 for DM firmware logs, configure DMA controllers with TI SCI references, and update OSPI0 register mapping. Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
2026-02-23Merge tag 'v2026.04-rc3' into nextTom Rini
Prepare v2026.04-rc3
2026-02-23Prepare v2026.04-rc3v2026.04-rc3Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-23fs/squashfs: fix heap buffer overflow in sqfs_frag_lookup()Eric Kilmer
sqfs_frag_lookup() reads a 16-bit metadata block header whose lower 15 bits encode the data size. Unlike sqfs_read_metablock() in sqfs_inode.c, this function does not validate that the decoded size is within SQFS_METADATA_BLOCK_SIZE (8192). A malformed SquashFS image can set the size field to any value up to 32767, causing memcpy to write past the 8192-byte 'entries' heap buffer. Add the same bounds check used by sqfs_read_metablock(): reject any metadata block header with SQFS_METADATA_SIZE(header) exceeding SQFS_METADATA_BLOCK_SIZE. Found by fuzzing with libFuzzer + AddressSanitizer. Signed-off-by: Eric Kilmer <eric.kilmer@trailofbits.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2026-02-20spl: fix stack placement in spl_relocate_stack_gd()Ronald Wahl
Currently when CONFIG_SPL_STACK_R and CONFIG_SPL_SYS_MALLOC_SIMPLE is enabled then spl_relocate_stack_gd() will setup a layout where the stack lays inside the heap and grows down to heap start. Also the global data is part of the heap. This can lead to corruption of stack and global data. The current layout is: 0x0 +-------------+ . . . . gd->malloc_base +- - - - - - -+ | |\ | HEAP/STACK | \ | | } SPL_STACK_R_MALLOC_SIMPLE_LEN gd->start_addr_sp +- - - - - - -+ / (gd->malloc_limit) | GLOBAL DATA |/ CONFIG_SPL_STACK_R_ADDR +-------------+ The above broken layout was actually introduced with commit adc421e4cee8 ("arm: move gd handling outside of C code"). This commit changes the layout so that the stack is below the heap and the global data. It is now similar to the one before relocation: 0x0+-------------+ . . . . +- - - - - - -+ | | | STACK | | | gd->start_addr_sp +-------------+ | GLOBAL DATA | gd->malloc_base +-------------+ | |\ | HEAP | } SPL_STACK_R_MALLOC_SIMPLE_LEN | |/ (gd->malloc_limit) CONFIG_SPL_STACK_R_ADDR +-------------+ Fixes: adc421e4cee8 ("arm: move gd handling outside of C code") Cc: Tom Rini <trini@konsulko.com> Cc: Anshul Dalal <anshuld@ti.com> Cc: Leo Yu-Chi Liang <ycliang@andestech.com> Cc: Dhruva Gole <d-gole@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Ronald Wahl <ronald.wahl@legrand.com>
2026-02-20defconfigs: Remove default COFNIG_SPL_LDSCRIPT valueTom Rini
These three platforms set CONFIG_SPL_LDSCRIPT value to what the default value for the question is, once evaluated. Remove this unnecessary line. Reviewed-by: Heiko Schocher <hs@nabladev.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2026-02-20board: ti: am62ax: tifs-rm-cfg.yaml: Add C7x resource allocation entriesSparsh Kumar
Update am62ax and am62dx tifs-rm-cfg with allocation entries for C7x core to match with their rm-cfg. Following updates are added for C7x: - Share split BCDMA tx and rx channels between DM R5 and C7x. - Share rings for split BCDMA tx and rx channels between DM R5 and C7x. - Add global events and virtual interrupts for C7x. Fixes: 01e01277538a ("am62a: yaml: Add board configs for AM62ax") Signed-off-by: Sparsh Kumar <sparsh-kumar@ti.com> Signed-off-by: Paresh Bhagat <p-bhagat@ti.com>
2026-02-20spi: add support for ISSI IS25WP02GG flashJeffrey Yu
This patch adds support for the ISSI IS25WP02GG QSPI NOR flash device. Tested on the Versal VMK180 board in dual-parallel QSPI configuration. Signed-off-by: jeffrey yu <jeyu@issi.com>
2026-02-20mtd: spi-nor-ids: Add Fujitsu MB85RS256TY FRAMChristoph Reiter
This part is an FRAM, but can be used through the spi-nor generic code. Signed-off-by: christoph.reiter@evk.biz
2026-02-20board: ti: am64,j721*: use correct fdt if eeprom detection failsAnshul Dalal
We currently provide default board names for each board in their respective evm.c file. However for custom boards, this behaviour overwrites the default DT as set in the defconfig (CONFIG_DEFAULT_FDT_FILE or CONFIG_DEFAULT_DEVICE_TREE). This patch changes the default name to be NULL which prevents this overwrite and allows ti_set_fdt_env to instead fallback to the correct DT as set in Kconfig. Signed-off-by: Anshul Dalal <anshuld@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
2026-02-20arm: mach-k3: j722s: Update SoC data to add wake-up I2C deviceChintan Vankar
Update dev-data and clk-data to include wake-up I2C device for J722s. Signed-off-by: Chintan Vankar <c-vankar@ti.com> Tested-by: Richard Genoud <richard.genoud@bootlin.com>
2026-02-18Merge patch series "bootcount: Small clean-up and fix, and dm_i2c ↵Tom Rini
single-word support" Niko Mauno <niko.mauno@vaisala.com> says: In this series, we first introduce a clean-up where we switch to use predefined bit masks instead of hard-coded values for count and magic halves in the single-word (32-bit) boot count scheme. Then we fix a case of missing boot count value masking in single-word scenario in bootcount.c, which allowed clobbering of the magic half when storing the value. With this change the clobbering preventing behavior becomes consistent with existing single word bootcount storing implementations in bootcount_at91.c and bootcount_davinci.c. Finally, we enable the DM I2C bootcount driver to work also in single word (4 byte) mode, in addition to the pre-existing half-word (2 byte) mode. By default the driver still operates in half word mode as so far, but can now be used alternatively in single word mode by adding 'size = <0x4>;' in the associated device tree node. Link: https://lore.kernel.org/r/cover.1770197302.git.niko.mauno@vaisala.com
2026-02-18bootcount: dm_i2c: Support also single word modeNiko Mauno
In addition to pre-existing half-word (2 byte) mode, add support for the driver to work also in single word (4 byte) mode by adding 'size = <0x4>;' in the device tree node. Signed-off-by: Niko Mauno <niko.mauno@vaisala.com>
2026-02-18bootcount: Fix potential clobbering issueNiko Mauno
When storing the single word bootcount value, apply the bootcount count mask to prevent clobbering the magic half of the value. Signed-off-by: Niko Mauno <niko.mauno@vaisala.com>
2026-02-18bootcount: Use predefined count/magic bit masksNiko Mauno
Use predefined bit masks in operations where only the magic half or only the count half of the 32-bit value are processed. Signed-off-by: Niko Mauno <niko.mauno@vaisala.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2026-02-18Merge patch series "test: cmd: Add test for zip/unzip/gzwrite commands"Tom Rini
Marek Vasut <marek.vasut+renesas@mailbox.org> says: Enable zip command in sandbox so it is always build tested. Add simple test for zip/unzip/gzwrite commands so they are unit tested. Link: https://lore.kernel.org/r/20260205014153.218621-1-marek.vasut+renesas@mailbox.org
2026-02-18test: cmd: Add test for zip/unzip/gzwrite commandsMarek Vasut
Add simple test for zip/unzip/gzwrite commands. The test works as follows. First, create three buffers with a bit of space between each of them, fill them with random data, then compress data in buffer 1 into buffer 2, decompress data in buffer 2 either directly into buffer 3 or into MMC 1 and then read them back into buffer 3, and finally compare buffer 1 and buffer 3, they have to be identical. The buffers are filled with random data to detect out of bounds writes. Test for various sizes, both small and large and unaligned. The test uses ut_assert_skip_to_line() to skip over gzwrite progress bar. Since the progress bar updates fill up the console record buffer, increase the size of it to compensate. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-18configs: sandbox: Enable zip commandMarek Vasut
What is not being built and tested in CI, breaks. Enable the 'zip' command in sandbox to get it build tested in preparation for an actual unit test. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-02-18arm: dts: k3-am64-phycore-som-ddr4: Update DDR timingsWadim Egorov
Update DDR timings to increase stability in higher temperature ranges. Update DDR settings: - SysConfig DDR tool v0.09.05 - Package: ALV - Extended temperature range -40C to 105C - Lower tREFI (ns) to 3900 Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Tested-by: Daniel Schultz <d.schultz@phytec.de>
2026-02-18Merge patch series "arm: dts: mt7622: use generic node names"Tom Rini
David Lechner <dlechner@baylibre.com> says: While compile-testing things to make sure I wasn't breaking other platforms when making mach-wide changes for mediatek, I kept getting a warning about a a SPI controller node with the wrong name in mt7622.dtsi. The first patch addresses this. And since we are here, I added a second patch to generic names in general in that file even if they aren't causing warnings. Link: https://lore.kernel.org/r/20260209-mtk-dtb-fix-spi-bus-bridge-warning-v1-0-84e3e2d8352d@baylibre.com
2026-02-18arm: dts: mt7622: Use generic node namesDavid Lechner
Replace node names in mt7622.dtsi with generic names. This makes it more consistent with the upstream bindings. Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-02-18arm: dts: mt7622: Fix SPI bus bridge warningDavid Lechner
Change SPI node name to generic "spi" in mt7622.dtsi. This fixes the following compile warning: w+../arch/arm/dts/mt7622.dtsi:56.22-65.4: Warning (spi_bus_bridge): /snor@11014000: node name for SPI buses should be 'spi' w+arch/arm/dts/mt7622-rfb.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge' Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-02-18pinctrl: mediatek: set MT798x rev as MTK_PINCTRL_V1Shiji Yang
The MT798x series SoCs have IES regiter definitions. They should belong to the pinctrl v1 revision. Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
2026-02-18pinctrl: mediatek: add pinctrl driver for MT8195Chris-QJ Chen
Add support for MT8195 pinctrl. The driver is based on the kernel one. Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com> Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18Merge patch series "Add MT8195 support"Tom Rini
Julien Stephan <jstephan@baylibre.com> says: This series adds basic support for Mediatek soc MT8195: - clock driver - watchdog - add a new macro helper to define gate clock. Other driver can be cleaned later to use the new macro Other driver will be added later. It will also serve as basis for board support such as MT8395_EVK based on MT8195. Link: https://lore.kernel.org/r/20260202-add-mt8195-clock-support-v1-0-5d03495246b9@baylibre.com
2026-02-18clk: mediatek: add MT8195 clock driverChris-QJ Chen
The following clocks have been added for MT8195 SoC: apmixedsys, topckgen, infracfg These clocks driver are based on the ones present in the kernel: drivers/clk/mediatek/clk-mt8195-* Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com> Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18clk: mediatek: implement GATE_FLAGS macroJulien Stephan
Add helper macro for mtk_gate, the same way, there are macros for FIXED_CLK, MUX and FACTOR. Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18arm: mediatek: add support for MediaTek MT8195 SoCJulien Stephan
This adds basic support for MediaTek MT8195 SoC. Add watchdog support by adding upstream compatible string. Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18Merge patch series "clk: mediatek: mt8188: fix clocks"Tom Rini
Julien Stephan <jstephan@baylibre.com> says: I recently submitted the clock driver for MT8188. I naively submitted a driver that was ported from the kernel driver, and mostly work to boot a kernel. Recently David Lechner, added support for the clk dump command for Mediatek clock drivers, so I used it to check the MT8188 and found several issues fixed on this series: - removed topckgen_cg, gates are now part of topckgen - fixed several parents clocks - added missing fixed clocks While at it, I also refactored a bit the driver to improve readability, and future additions to it. Link: https://lore.kernel.org/r/20260202-mt8188-fix-clock-v2-0-b39bddfcac66@baylibre.com
2026-02-18clk: mediatek: mt8188: refactor driver to improve readabilityJulien Stephan
Refactor some part of the driver to improve readability and future additions: - use CLK_TOP_NR_CLK for added clocks - rename the id map to make it more clear that the map applies to top clocks only - refactor the id map to improve readability - xtal2_rate is only used for PLL clocks, so only the apmixedsys clock tree needs it. Remove it elsewhere. Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18clk: mediatek: mt8188: fix some clock parentsJulien Stephan
Fix a number of clock parent definitions for MT8188 clocks. Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18clk: mediatek: mt8188: add missing fixed clockJulien Stephan
CLK_TOP_CLK13M was missing, add it. Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18clk: mediatek: mt8188: fix circular clock dependencyJulien Stephan
FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 3) --> CLK_TOP_APLL1_D4 declares CLK_TOP_APLL1 as it's parents MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7) --> CLK_TOP_APLL1 declares apll1_parents as it's parents static const int apll1_parents[] = { CLK_TOP_CLK26M, CLK_TOP_APLL1_D4 }; --> CLK_TOP_APLL1_D4 is a parent of CLK_TOP_APLL1 Fix this, by correctly setting CLK_TOP_APLL1_DX parent to CLK_APMIXED_APLLX Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18clk: mediatek: mt8188: remove separate topckgen-cg driverJulien Stephan
Remove the separate topckgen-cg driver for handling clock gates in the topckgen address space. Commit 8aeeeff50d46 ("clk: mediatek: allow gates in topckgen drivers") added support for gates in topckgen driver. This commit fixes MT8188 driver, the same way commit ba207d7f54f9 ("clk: mediatek: mt8365: remove separate topckgen-cg driver") does for MT8365. Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18board: mediatek: add MT8370 EVK board supportJulien Stephan
This adds support for the MT8370 EVK board with the following features enabled/tested: Boot, UART, Watchdog and MMC. MT8370 is based on MT8188. Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Signed-off-by: Julien Stephan <jstephan@baylibre.com>
2026-02-18Merge patch series "arm: mediatek: clean up some redundant board init"Tom Rini
David Lechner <dlechner@baylibre.com> says: Before adding more targets, we take a moment to clean up some some redundant code in existing Mediatek SoC support. The first three patches are removing no-op functions. The last patch generalizes the mem_map code so that it can be shared between all Mediatek ARMv8 SoCs. Link: https://lore.kernel.org/r/20260209-mtk-mach-clean-up-duplicates-v2-0-e3b22282c74d@baylibre.com
2026-02-18arm: mediatek: add CONFIG_MTK_MEM_MAP_DDR_BASE_PHYDavid Lechner
Add a CONFIG_MTK_MEM_MAP_DDR_BASE_PHY variable to specify the DDR base physical address for the Mediatek ARMv8 memory map. This will be used by MT8196 in the future which has a different DDR base address than other Mediatek SoCs. Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
2026-02-18arm: mediatek: consolidate ARMv8 memory mapsDavid Lechner
Consolidate all mem_map definitions for MediaTek ARMv8 platforms into a single file. The size of the DDR and MMIO regions can vary, so Kconfig options are added to configure them by target. Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-02-18board/mediatek: move EVK MAINTAINERS to common fileDavid Lechner
Move the mt8365_evk and mt8390_evk MAINTAINERS files to a common MAINTAINERS file. We will be deleting the board-specific directories soon but we need to keep the MAINTAINERS for the defconfig entries. Signed-off-by: David Lechner <dlechner@baylibre.com>
2026-02-18arm: mediatek: make mtk_pll_early_init() staticDavid Lechner
Make the mtk_pll_early_init() function static in several files. It is only used within those files, so there is no need to have it in the global namespace. Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
2026-02-18arm: mediatek: mt8183: remove unused functionDavid Lechner
Remove the mtk_pll_early_init() function as it is not used anywhere. Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
2026-02-18board: mediatek: mt8390_evk: remove empty board_init()David Lechner
Remove empty board_init() function and adjust defconfig to not require it. Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
2026-02-18arm: mediatek: use default weak mtk_soc_early_init()David Lechner
Add a weak default implementation of mtk_soc_early_init() in spl.c to avoid having to define it in every SoC init.c file that does not need any additional early initialization. The init.h header file is no longer needed in this case and is removed. Signed-off-by: David Lechner <dlechner@baylibre.com>
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