diff options
| author | Julien Stephan <jstephan@baylibre.com> | 2026-02-02 13:41:50 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2026-02-18 11:59:32 -0600 |
| commit | 6354f83f43f7d2c1b76a17f9b5629a1af7b7916a (patch) | |
| tree | 51dbcb8cdd92a131d2e79a599f521fe582efebcb | |
| parent | a04835c0e929c04403b01b50e1dd966eb42e5004 (diff) | |
clk: mediatek: mt8188: fix circular clock dependency
FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 3)
--> CLK_TOP_APLL1_D4 declares CLK_TOP_APLL1 as it's parents
MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7)
--> CLK_TOP_APLL1 declares apll1_parents as it's parents
static const int apll1_parents[] = {
CLK_TOP_CLK26M,
CLK_TOP_APLL1_D4
};
--> CLK_TOP_APLL1_D4 is a parent of CLK_TOP_APLL1
Fix this, by correctly setting CLK_TOP_APLL1_DX parent to CLK_APMIXED_APLLX
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8188.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index 4317dd253bb..f306cce1f5b 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -148,13 +148,13 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_UNIVPLL_192M_D10, CLK_TOP_UNIVPLL_192M, 1, 10), FACTOR1(CLK_TOP_UNIVPLL_192M_D16, CLK_TOP_UNIVPLL_192M, 1, 16), FACTOR1(CLK_TOP_UNIVPLL_192M_D32, CLK_TOP_UNIVPLL_192M, 1, 32), - FACTOR1(CLK_TOP_APLL1_D3, CLK_TOP_APLL1, 1, 3), - FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4), - FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3), - FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4), - FACTOR1(CLK_TOP_APLL3_D4, CLK_TOP_APLL3, 1, 4), - FACTOR1(CLK_TOP_APLL4_D4, CLK_TOP_APLL4, 1, 4), - FACTOR1(CLK_TOP_APLL5_D4, CLK_TOP_APLL5, 1, 4), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL3_D4, CLK_APMIXED_APLL3, 1, 4), + FACTOR0(CLK_TOP_APLL4_D4, CLK_APMIXED_APLL4, 1, 4), + FACTOR0(CLK_TOP_APLL5_D4, CLK_APMIXED_APLL5, 1, 4), FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4), FACTOR1(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1, 2), FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5), |