From c2b75a5353aec990bbb8bd53737d39b497a7bdaa Mon Sep 17 00:00:00 2001 From: Jjian Zhou Date: Mon, 13 Oct 2025 14:31:35 +0800 Subject: dt-bindings: mailbox: mediatek,mt8196-vcp-mbox: add mtk vcp-mbox document The MTK VCP mailbox enables the SoC to communicate with the VCP by passing messages through 64 32-bit wide registers. It has 32 interrupt vectors in either direction for signalling purposes. This adds a binding for Mediatek VCP mailbox. Signed-off-by: Jjian Zhou Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jassi Brar --- .../bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml new file mode 100644 index 000000000000..7b1c5165e64e --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-vcp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Video Companion Processor (VCP) mailbox + +maintainers: + - Jjian Zhou + +description: + The MTK VCP mailbox enables the SoC to communicate with the VCP by passing + messages through 64 32-bit wide registers. It has 32 interrupt vectors in + either direction for signalling purposes. + +properties: + compatible: + enum: + - mediatek,mt8196-vcp-mbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + mailbox@31b80000 { + compatible = "mediatek,mt8196-vcp-mbox"; + reg = <0x31b80000 0x1000>; + interrupts = ; + #mbox-cells = <0>; + }; -- cgit v1.2.3 From d96ebba37b7d08a4d7d5f4b992b4400e6e7b8fa1 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Tue, 21 Oct 2025 23:32:30 -0700 Subject: dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for Kaanapali Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm Kaanapali, which is compatible with X1E80100, use fallback to indicate this. Signed-off-by: Jingyi Wang Acked-by: Rob Herring (Arm) Signed-off-by: Jassi Brar --- Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 9122c3d2dc30..9e91247c521a 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - qcom,glymur-cpucp-mbox + - qcom,kaanapali-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: - qcom,x1e80100-cpucp-mbox -- cgit v1.2.3 From 74ff7036589a8b7708b7cdad76d1aff1a842e5ba Mon Sep 17 00:00:00 2001 From: Pierre-Henry Moussay Date: Mon, 17 Nov 2025 15:46:54 +0000 Subject: dt-bindings: mbox: add pic64gx mailbox compatibility to mpfs mailbox pic64gx mailbox is compatible with mpfs mailbox, even if the mailbox consumer is not - the underlying communication mechanism is the same. Signed-off-by: Pierre-Henry Moussay Signed-off-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Signed-off-by: Jassi Brar --- .../devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml index 1332aab9a888..5f2ec74c1b29 100644 --- a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml @@ -11,7 +11,11 @@ maintainers: properties: compatible: - const: microchip,mpfs-mailbox + oneOf: + - items: + - const: microchip,pic64gx-mailbox + - const: microchip,mpfs-mailbox + - const: microchip,mpfs-mailbox reg: oneOf: -- cgit v1.2.3 From dac2b98ede6c29f01dec95e88fef59e5138bd3a4 Mon Sep 17 00:00:00 2001 From: Harini T Date: Fri, 9 Jan 2026 11:52:59 +0530 Subject: dt-bindings: mailbox: xlnx,zynqmp-ipi-mailbox: Document msg region requirement Add description clarifying that for Versal IPI mailboxes, both host and remote agents must have the "msg" register region defined for successful message passing. Without both, only notification-based communication works. Signed-off-by: Harini T Acked-by: Rob Herring (Arm) Signed-off-by: Jassi Brar --- .../devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml index 04d6473d666f..a5205ee5ad0f 100644 --- a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml @@ -11,6 +11,17 @@ description: | messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI agent owns registers used for notification and buffers for message. + For Versal devices, there are two types of IPI channels: + - Buffered channels: Support message passing and require the "msg" + register region to be present on both the host and remote IPI agents. + - Buffer-less channels: Support notification only and do not require the + "msg" register region. For these channels, the "msg" region should be + omitted. + + For message passing, both the host and remote IPI agents must define the "msg" + register region. If either agent omits the "msg" region, only notification + based communication is possible. + +-------------------------------------+ | Xilinx ZynqMP IPI Controller | +-------------------------------------+ -- cgit v1.2.3 From 0856aed508878c6208cf17c75361317287101b3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Otto=20Pfl=C3=BCger?= Date: Sat, 10 Jan 2026 16:43:35 +0100 Subject: dt-bindings: mailbox: sprd: add compatible for UMS9230 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a compatible string for the mailbox controller found in the UMS9230 SoC. Signed-off-by: Otto Pflüger Acked-by: Krzysztof Kozlowski Signed-off-by: Jassi Brar --- Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml index b526f9c0c272..bf6ab4e7050c 100644 --- a/Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml @@ -16,6 +16,7 @@ properties: enum: - sprd,sc9860-mailbox - sprd,sc9863a-mailbox + - sprd,ums9230-mailbox reg: items: -- cgit v1.2.3