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2025-11-18drm/msm/adreno: Add MMU fault handler to adreno_gpu_funcAkhil P Oommen
Move MMU fault handler for each generation to adreno function list. This will help to use common code for mmu pagefault handler registration between a6x/a7x and a8x layer. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689007/ Message-ID: <20251118-kaana-gpu-support-v4-8-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-11-18drm/msm/adreno: Move gbif_halt() to adreno_gpu_funcAkhil P Oommen
Move the gbif halt fn to adreno_gpu_func so that we can call different implementation from common code. This will come handy when we implement A8x layer. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689005/ Message-ID: <20251118-kaana-gpu-support-v4-7-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-11-18drm/msm/adreno: Move adreno_gpu_func to catalogueAkhil P Oommen
In A6x family (which is a pretty big one), there are separate adreno_func definitions for each sub-generations. To streamline the identification of the correct struct for a gpu, move it to the catalogue and move the gpu_init routine to struct adreno_gpu_funcs. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689003/ Message-ID: <20251118-kaana-gpu-support-v4-6-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-11-18drm/msm/adreno: Common-ize PIPE definitionsAkhil P Oommen
Newer gen's introduce pipe enums which do not exist on older gens, but the numeric values do not conflict. IOW, they are backward compatible. So move its definition to adreno_common.xml. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689001/ Message-ID: <20251118-kaana-gpu-support-v4-5-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-11-18drm/msm/a6xx: Skip dumping SCRATCH registersAkhil P Oommen
Crashdec doesn't require SCRATCH registers anymore for a6xx and newer architectures. So skip dumping them during recovery. Suggested-by: Rob Clark <rob.clark@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689000/ Message-ID: <20251118-kaana-gpu-support-v4-4-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-11-18drm/msm/a6xx: Fix the gemnoc workaroundAkhil P Oommen
Correct the register offset and enable this workaround for all A7x and newer GPUs to match the recommendation. Also, downstream does this w/a after moving the fence to allow mode. So do the same. Fixes: dbfbb376b50c ("drm/msm/a6xx: Add A621 support") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688997/ Message-ID: <20251118-kaana-gpu-support-v4-3-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-11-18drm/msm/a6xx: Flush LRZ cache before PT switchAkhil P Oommen
As per the recommendation, A7x and newer GPUs should flush the LRZ cache before switching the pagetable. Update a6xx_set_pagetable() to do this. While we are at it, sync both BV and BR before issuing a CP_RESET_CONTEXT_STATE command, to match the downstream sequence. Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688995/ Message-ID: <20251118-kaana-gpu-support-v4-2-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-11-18drm/msm/a6xx: Fix out of bound IO access in a6xx_get_gmu_registersAkhil P Oommen
REG_A6XX_GMU_AO_AHB_FENCE_CTRL register falls under GMU's register range. So, use gmu_write() routines to write to this register. Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state") Cc: stable@vger.kernel.org Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/688993/ Message-ID: <20251118-kaana-gpu-support-v4-1-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2025-11-18drm/msm/registers: Fix encoding fields in 64b registersRob Clark
Based on mesa commit 3f70b0578402 ("freedreno/registers: Fix encoding fields in 64b registers"), but with some fixes to not skip emitting interrupt enum values. v2: Don't append "ull" to 32b reg MASK defines, to avoid printf format conversion warnings all over the place Co-developed-by: Connor Abbott <cwabbott0@gmail.com> Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689141/ Message-ID: <20251118152952.226510-1-robin.clark@oss.qualcomm.com>
2025-11-18mmc: renesas_sdhi: Add suspend/resume hooksClaudiu Beznea
Add suspend/resume hooks which assert/deassert the reset signals, along with forcing runtime suspend/resume. This allows using the driver in scenarios where the resume is done with the help of bootloader and the bootloader disables the SDHI clocks, resets, IRQs before passing execution to Linux. Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18mmc: renesas_sdhi: Switch to SYSTEM_SLEEP_PM_OPS()/RUNTIME_PM_OPS() and pm_ptr()Claudiu Beznea
SET_SYSTEM_SLEEP_PM_OPS() and SET_RUNTIME_PM_OPS() require __maybe_unused or #ifdefs protection against unused function warnings. The usage of pm_ptr() and SYSTEM_SLEEP_PM_OPS()/RUNTIME_PM_OPS() allows the compiler to see the functions, thus suppressing the warning. Drop the #ifdefs. Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18mmc: renesas_sdhi: Deassert the reset signal on probeClaudiu Beznea
Deassert the reset signal of the SDHI controller during probe to avoid relying on the previous bootloaders. Without deasserting the reset signal, the SDHI controller will not function. Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18mmc: meson-mx-sdio: Ignore disabled "mmc-slot" child-nodesMartin Blumenstingl
The meson-mx-sdio (and mmc core) only support one MMC/SD/SDIO slot (device) per host. Thus having multiple mmc-slot nodes (one for the up to three supported slots with one device each on the meson-mx-sdio hardware) can be problematic. Allow specifying all slots (with their respective device) connected to the meson-mx-sdio hardware in device-tree, while making sure that only the enabled one(s) are actually considered by the driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18mmc: meson-mx-sdio: Fix indentation in meson_mx_mmc_irq_thread()Martin Blumenstingl
Keep the second line with arguments for dma_unmap_sg() aligned. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18mmc: meson-mx-sdio: Use dev_err_probe() where appropriateMartin Blumenstingl
This streamlines probe error handling / logging with other drivers. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18mmc: meson-mx-sdio: Use devm_mmc_alloc_host() helperBinbin Zhou
Use new function devm_mmc_alloc_host() to simplify the code. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18mmc: meson-mx-sdio: Refactor internal clock initializationMartin Blumenstingl
Use modern common clock framework helpers for simplifying the clock controller management: - switch to struct clk_hw for internal clocks and only get the "cfg_div_clk" (which has to be managed at runtime) as struct clk using devm_clk_hw_get_clk() which is then the only clock used by struct meson_mx_mmc_host. - use CLK_HW_INIT_FW_NAME and CLK_HW_INIT_HW helper macros for simpler init data initialization - keep the clock controller memory allocation separate to prevent a potential use-after-free because struct meson_mx_mmc_host_clkc is free'd before controller_dev Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18mmc: meson-mx-sdio: Use devm_clk_get_enabled()Martin Blumenstingl
This simplifies the code. No functional changes intended. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18mmc: meson-mx-sdio: Switch to regmap for register accessMartin Blumenstingl
Switch the driver over to use regmap to access the registers. This makes it consistent with the other Amlogic MMC drivers. No functional changes intended. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-11-18gve: Add Rx HWTS metadata to AF_XDP ZC modeTim Hostetler
By overlaying the struct gve_xdp_buff on top of the struct xdp_buff_xsk that AF_XDP utilizes, the driver records the 32 bit timestamp via the completion descriptor and the cached 64 bit NIC timestamp via gve_priv. The driver's implementation of xmo_rx_timestamp extends the timestamp to the full and up to date 64 bit timestamp and returns it to the user. gve_rx_xsk_dqo is modified to accept a pointer to the completion descriptor and no longer takes a buf_len explicitly as it can be pulled out of the descriptor. With this patch gve now supports bpf_xdp_metadata_rx_timestamp. Signed-off-by: Tim Hostetler <thostet@google.com> Reviewed-by: Willem de Bruijn <willemb@google.com> Reviewed-by: Harshitha Ramamurthy <hramamurthy@google.com> Signed-off-by: Joshua Washington <joshwash@google.com> Link: https://patch.msgid.link/20251114211146.292068-5-joshwash@google.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-11-18gve: Prepare bpf_xdp_metadata_rx_timestamp supportTim Hostetler
Support populating XDP RX metadata with hardware RX timestamps. This patch utilizes the same underlying logic to calculate hardware timestamps as the regular RX path. xdp_metadata_ops is registered with the net_device in a future patch. gve_rx_calculate_hwtstamp was pulled out so as to not duplicate logic between gve_xdp_rx_timestamp and gve_rx_hwtstamp. Signed-off-by: Tim Hostetler <thostet@google.com> Reviewed-by: Willem de Bruijn <willemb@google.com> Reviewed-by: Harshitha Ramamurthy <hramamurthy@google.com> Signed-off-by: Joshua Washington <joshwash@google.com> Link: https://patch.msgid.link/20251114211146.292068-4-joshwash@google.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-11-18gve: Wrap struct xdp_buffTim Hostetler
RX timestamping will need to keep track of extra temporary information per-packet. In preparation for this, introduce gve_xdp_buff to wrap the xdp_buff. This is similar in function to stmmac_xdp_buff and ice_xdp_buff. Signed-off-by: Tim Hostetler <thostet@google.com> Reviewed-by: Willem de Bruijn <willemb@google.com> Reviewed-by: Harshitha Ramamurthy <hramamurthy@google.com> Signed-off-by: Joshua Washington <joshwash@google.com> Link: https://patch.msgid.link/20251114211146.292068-3-joshwash@google.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-11-18gve: Move ptp_schedule_worker to gve_init_clockTim Hostetler
Previously, gve had been only initializing ptp aux work when hardware timestamping was initialized through ndo_hwtsatmp_set. As this patch series introduces XDP hardware timestamp metadata which will require the ptp aux work, the work can't be gated on the kernel_hwtstamp_config being set and must be initialized elsewhere. For simplicity, ptp_schedule_worker is invoked right after the ptp_clock is registered with the kernel (which happens during gve_probe or following reset). The worker is scheduled in GVE_NIC_TS_SYNC_INTERVAL_MS as the synchronous call to gve_clock_nic_ts_read makes the worker redundant if scheduled immediately. If gve cannot read the device clock immediately, it errors out of gve_init_clock. Signed-off-by: Tim Hostetler <thostet@google.com> Reviewed-by: Willem de Bruijn <willemb@google.com> Reviewed-by: Harshitha Ramamurthy <hramamurthy@google.com> Signed-off-by: Joshua Washington <joshwash@google.com> Link: https://patch.msgid.link/20251114211146.292068-2-joshwash@google.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-11-18cpufreq: intel_pstate: Eliminate some code duplicationRafael J. Wysocki
To eliminate some code duplication from the intel_pstate driver, move the core_get_val() function body to a new function called get_perf_ctl_val() and make both core_get_val() and atom_get_val() invoke it to carry out the same computation. No intentional functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Link: https://patch.msgid.link/2829273.mvXUDI8C0e@rafael.j.wysocki
2025-11-18PM: sleep: core: Fix runtime PM enabling in device_resume_early()Rafael J. Wysocki
Runtime PM should only be enabled in device_resume_early() if it has been disabled for the given device by device_suspend_late(). Otherwise, it may cause runtime PM callbacks to run prematurely in some cases which leads to further functional issues. Make two changes to address this problem. First, reorder device_suspend_late() to only disable runtime PM for a device when it is going to look for the device's callback or if the device is a "syscore" one. In all of the other cases, disabling runtime PM for the device is not in fact necessary. However, if the device's callback returns an error and the power.is_late_suspended flag is not going to be set, enable runtime PM so it only remains disabled when power.is_late_suspended is set. Second, make device_resume_early() only enable runtime PM for the devices with the power.is_late_suspended flag set. Fixes: 443046d1ad66 ("PM: sleep: Make suspend of devices more asynchronous") Reported-by: Rose Wu <ya-jou.wu@mediatek.com> Closes: https://lore.kernel.org/linux-pm/70b25dca6f8c2756d78f076f4a7dee7edaaffc33.camel@mediatek.com/ Cc: 6.16+ <stable@vger.kernel.org> # 6.16+ Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://patch.msgid.link/12784270.O9o76ZdvQC@rafael.j.wysocki
2025-11-18powercap: intel_rapl: Add support for Nova Lake processorsKaushlendra Kumar
Add RAPL support for Intel Nova Lake and Nova Lake L processors using the core defaults configuration. Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com> [ rjw: Subject and changelog edits, rebase ] Link: https://patch.msgid.link/20251028101814.3482508-1-kaushlendra.kumar@intel.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-11-18net: phy: micrel: lan8814: Enable in-band auto-negotiationHoratiu Vultur
The lan8814 supports two interfaces towards the host (QSGMII and QUSGMII). Currently the lan8814 disables the auto-negotiation towards the host side. So, extend this to allow to configure to use in-band auto-negotiation. I have tested this only with the QSGMII interface. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Link: https://patch.msgid.link/20251114084224.3268928-1-horatiu.vultur@microchip.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-11-18pinctrl: cherryview: Convert to use intel_gpio_add_pin_ranges()Andy Shevchenko
Driver is ready to use intel_gpio_add_pin_ranges() directly instead of custom approach. Convert it now. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-18pinctrl: intel: Export intel_gpio_add_pin_ranges()Andy Shevchenko
Export intel_gpio_add_pin_ranges() for reuse in other drivers. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-11-18loop: add hint for handling aio via IOCB_NOWAITMing Lei
Add hint for using IOCB_NOWAIT to handle loop aio command for avoiding to cause write(especially randwrite) perf regression on sparse backed file. Try IOCB_NOWAIT in the following situations: - backing file is block device OR - READ aio command OR - there isn't any queued blocking async WRITEs, because NOWAIT won't cause contention with blocking WRITE, which often implies exclusive lock With this simple policy, perf regression of randwrite/write on sparse backing file is fixed. Link: https://lore.kernel.org/dm-devel/7d6ae2c9-df8e-50d0-7ad6-b787cb3cfab4@redhat.com/ Signed-off-by: Ming Lei <ming.lei@redhat.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-11-18loop: try to handle loop aio command via NOWAIT IO firstMing Lei
Try to handle loop aio command via NOWAIT IO first, then we can avoid to queue the aio command into workqueue. This is usually one big win in case that FS block mapping is stable, Mikulas verified [1] that this way improves IO perf by close to 5X in 12jobs sequential read/write test, in which FS block mapping is just stable. Fallback to workqueue in case of -EAGAIN. This way may bring a little cost from the 1st retry, but when running the following write test over loop/sparse_file, the actual effect on randwrite is obvious: ``` truncate -s 4G 1.img #1.img is created on XFS/virtio-scsi losetup -f 1.img --direct-io=on fio --direct=1 --bs=4k --runtime=40 --time_based --numjobs=1 --ioengine=libaio \ --iodepth=16 --group_reporting=1 --filename=/dev/loop0 -name=job --rw=$RW ``` - RW=randwrite: obvious IOPS drop observed - RW=write: a little drop(%5 - 10%) This perf drop on randwrite over sparse file will be addressed in the following patch. BLK_MQ_F_BLOCKING has to be set for calling into .read_iter() or .write_iter() which might sleep even though it is NOWAIT, and the only effect is that rcu read lock is replaced with srcu read lock. Link: https://lore.kernel.org/linux-block/a8e5c76a-231f-07d1-a394-847de930f638@redhat.com/ [1] Signed-off-by: Ming Lei <ming.lei@redhat.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-11-18loop: move command blkcg/memcg initialization into loop_queue_workMing Lei
Move loop command blkcg/memcg initialization into loop_queue_work, and prepare for supporting to handle loop io command by IOCB_NOWAIT. Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Ming Lei <ming.lei@redhat.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-11-18loop: add lo_submit_rw_aio()Ming Lei
Refactor lo_rw_aio() by extracting the I/O submission logic into a new helper function lo_submit_rw_aio(). This further improves code organization by separating the I/O preparation, submission, and completion handling into distinct phases. Prepare for using NOWAIT to improve loop performance. Signed-off-by: Ming Lei <ming.lei@redhat.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-11-18loop: add helper lo_rw_aio_prep()Ming Lei
Add helper lo_rw_aio_prep() to separate the preparation phase(setting up bio vectors and initializing the iocb structure) from the actual I/O execution in the loop block driver. Prepare for using NOWAIT to improve loop performance. Signed-off-by: Ming Lei <ming.lei@redhat.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-11-18loop: add helper lo_cmd_nr_bvec()Ming Lei
Add lo_cmd_nr_bvec() and prepare for refactoring lo_rw_aio(). Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Ming Lei <ming.lei@redhat.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-11-18drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY ADnyaneshwar Bhadane
On PTL, no combo PHY is connected to PORT B. However, PORT B can still be used for Type-C and will utilize the C20 PHY for eDP over Type-C. In such configurations, VBTs also enumerate PORT B. This leads to issues where PORT B is incorrectly identified as using the C10 PHY, due to the assumption that returning true for PORT B in intel_encoder_is_c10phy() would not cause problems. From PTL's perspective, only PORT A/PHY A uses the C10 PHY. Update the helper intel_encoder_is_c10phy() to return true only for PORT A/PHY on PTL. v2: Change the condition code style for ptl/wcl Bspec: 72571,73944 Fixes: 9d10de78a37f ("drm/i915/wcl: C10 phy connected to port A and B") Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250922150317.2334680-4-dnyaneshwar.bhadane@intel.com (cherry picked from commit 8147f7a1c083fd565fb958824f7c552de3b2dc46) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-11-18drm/i915/display: Add definition for wcl as subplatformDnyaneshwar Bhadane
We will need to differentiate between WCL and PTL in intel_encoder_is_c10phy(). Since WCL and PTL use the same display architecture, let's define WCL as a subplatform of PTL to allow the differentiation. v2: Update commit message and reorder wcl define (Gustavo) Fixes: 3c0f211bc8fc ("drm/xe: Add Wildcat Lake device IDs to PTL list") Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250922150317.2334680-3-dnyaneshwar.bhadane@intel.com (cherry picked from commit 4dfaae643e59cf3ab71b88689dce1b874f036f00) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Rodrigo added Fixes tag when porting it to fixes]
2025-11-18drbd: turn bitmap I/O comments into regular block commentsSukrut Heroorkar
W=1 build warns because the bitmap I/O comments use '/**', which marks them as kernel-doc comments even though these functions do not document an external API. Convert these comments to regular block comments so kernel-doc no longer parses them. Signed-off-by: Sukrut Heroorkar <hsukrut3@gmail.com> Acked-by: Christoph Böhmwalder <christoph.boehmwalder@linbit.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-11-18drm/pcids: Split PTL pciids group to make wcl subplatformDnyaneshwar Bhadane
To form the WCL platform as a subplatform of PTL in definition, WCL pci ids are splited into saparate group from PTL. So update the pciidlist struct to cover all the pci ids. v2: - Squash wcl description in single patch for display and xe.(jani,gustavo) Fixes: 3c0f211bc8fc ("drm/xe: Add Wildcat Lake device IDs to PTL list") Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250922150317.2334680-2-dnyaneshwar.bhadane@intel.com (cherry picked from commit 32620e176443bf23ec81bfe8f177c6721a904864) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Rodrigo added the Fixes tag when porting it to fixes]
2025-11-18drm/mediatek: Fix CCORR mtk_ctm_s31_32_to_s1_n function issueJay Liu
if matrixbit is 11, The range of color matrix is from 0 to (BIT(12) - 1). Values from 0 to (BIT(11) - 1) represent positive numbers, values from BIT(11) to (BIT(12) - 1) represent negative numbers. For example, -1 need converted to 8191. so convert S31.32 to HW Q2.11 format by drm_color_ctm_s31_32_to_qm_n, and set int_bits to 2. Fixes: 738ed4156fba ("drm/mediatek: Add matrix_bits private data for ccorr") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Jay Liu <jay.liu@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20250921055416.25588-2-jay.liu@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2025-11-18mtd: spi-nor: core: Check read CR supportJakub Czapiga
Some SPI controllers like Intel's one on the PCI bus do not support opcode 35h. This opcode is used to read the Configuration Register on SPI-NOR chips that have 16-bit Status Register configured regardless of the controller support for it. Adding a check call in the setup step allows disabling use of the 35h opcode and falling back to the manual Status Registers management. Before: openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4 ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = -1 EOPNOTSUPP After: openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4 ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = 0 ioctl(4, MIXER_WRITE(5) or MEMLOCK, {start=0x1800000, length=0x800000}) = 0 Suggested-by: Adeel Arshad <adeel.arshad@intel.com> Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
2025-11-18mtd: spi-nor: micron-st: add TODO for fixing mt35xu02gcbaHaibo Chen
The MT35XU02GCBA flash device does not support chip erase, according to its datasheet. It supports die erase, which means the current driver implementation will likely need to be converted to use die erase. Furthermore, similar to the MT35XU01GBBA, the SPI_NOR_IO_MODE_EN_VOLATILE flag probably needs to be enabled. Currently no active contributor has access to this hardware so there is no way of testing the fixes. Add a TODO item on the flash entry so someone with the flash can test that the support is indeed broken and send the fixes. Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> [pratyush@kernel.org: refactor the comment and commit message to make the purpose of the comment clearer] Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
2025-11-18mtd: spi-nor: micron-st: add mt35xu01gbba supportHaibo Chen
mt35xu01gbba is similar with mt35xu512aba, but with two dies. mt35xu01gbba has SFDP and support 8D-8D-8D mode, but SFDP lack SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here. Besides, mt35xu01gbba do not support chip erase, but support die erase, so add that in late_init(). Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
2025-11-18mtd: spi-nor: micron-st: use SFDP of mt35xu512abaHaibo Chen
mt35xu512aba has SFDP, already contain the necessary information, so remove size and some flags here. Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
2025-11-18mtd: spi-nor: micron-st: move set_octal_dtr to late_init()Haibo Chen
Move params->set_octal_dtr from flash_info->fixups->default_init() to spi_nor_manufacturer-> fixups-> late_init(), this can cover all Micorn and ST chips without repeat in each chip's flash_info. Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
2025-11-18mtd: spi-nor: micron-st: rename the die_late_init functionsHaibo Chen
st_nor_two/four_die_late_init() also suit for micron chips, so rename to micron_st_nor_two/four_die_late_init(), and move these functions up, then micron can use these function without declaration. Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
2025-11-18spi: aspeed: Add AST2700 SoC support and Quad SPIMark Brown
Merge series from Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>: This series adds AST2700 support to the ASPEED FMC/SPI driver and bindings, introduces 64-bit address compatibility, and improves Quad SPI page programming behavior. It also implements AST2700-specific segment logic, where range adjustment is not required because the AST2700 SPI hardware controller already fixes decoding issues on the existing platforms and adopts an updated scheme.
2025-11-18ASoC: Intel: avs: Allow for NHLT configurationMark Brown
Merge series from Cezary Rojewski <cezary.rojewski@intel.com> From AudioDSP perspective, only gateway-related modules e.g.: Copier: Small set of changes providing new feature which the driver is already utilizing on the market - for its Long-Term-Support (LTS) devices. The goal is to cover systems which shipped with invalid Non HDAudio Link Table (NHLT) - not just the descriptors (headers), but cases where the hardware configuration is invalid too. The table is part of the ACPI tree and forcing BIOS updates is not a feasible solution. With the override, the topology file can carry the hardware configuration instead. From AudioDSP perspective, only gateway-related modules e.g.: Copier care about the procedure. To ensure correct order of operations when initializing such modules, the overrides take precedence over what's currently there in the NHLT.
2025-11-18net: ps3_gelic_net: handle skb allocation failuresFlorian Fuchs
Handle skb allocation failures in RX path, to avoid NULL pointer dereference and RX stalls under memory pressure. If the refill fails with -ENOMEM, complete napi polling and wake up later to retry via timer. Also explicitly re-enable RX DMA after oom, so the dmac doesn't remain stopped in this situation. Previously, memory pressure could lead to skb allocation failures and subsequent Oops like: Oops: Kernel access of bad area, sig: 11 [#2] Hardware name: SonyPS3 Cell Broadband Engine 0x701000 PS3 NIP [c0003d0000065900] gelic_net_poll+0x6c/0x2d0 [ps3_gelic] (unreliable) LR [c0003d00000659c4] gelic_net_poll+0x130/0x2d0 [ps3_gelic] Call Trace: gelic_net_poll+0x130/0x2d0 [ps3_gelic] (unreliable) __napi_poll+0x44/0x168 net_rx_action+0x178/0x290 Steps to reproduce the issue: 1. Start a continuous network traffic, like scp of a 20GB file 2. Inject failslab errors using the kernel fault injection: echo -1 > /sys/kernel/debug/failslab/times echo 30 > /sys/kernel/debug/failslab/interval echo 100 > /sys/kernel/debug/failslab/probability 3. After some time, traces start to appear, kernel Oopses and the system stops Step 2 is not always necessary, as it is usually already triggered by the transfer of a big enough file. Fixes: 02c1889166b4 ("ps3: gigabit ethernet driver for PS3, take3") Signed-off-by: Florian Fuchs <fuchsfl@gmail.com> Link: https://patch.msgid.link/20251113181000.3914980-1-fuchsfl@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-11-18net: qlogic/qede: fix potential out-of-bounds read in qede_tpa_cont() and ↵Pavel Zhigulin
qede_tpa_end() The loops in 'qede_tpa_cont()' and 'qede_tpa_end()', iterate over 'cqe->len_list[]' using only a zero-length terminator as the stopping condition. If the terminator was missing or malformed, the loop could run past the end of the fixed-size array. Add an explicit bound check using ARRAY_SIZE() in both loops to prevent a potential out-of-bounds access. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 55482edc25f0 ("qede: Add slowpath/fastpath support and enable hardware GRO") Signed-off-by: Pavel Zhigulin <Pavel.Zhigulin@kaspersky.com> Link: https://patch.msgid.link/20251113112757.4166625-1-Pavel.Zhigulin@kaspersky.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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