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2026-01-05drm/amd/display: Update function name to link_detect_connection_type_analogAlex Hung
[WHAT] Update function "link_detect_analog" to a more accurate name "link_detect_connection_type_analog". Suggested-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: sink EDID data null checkRichard Chiang
[Why] When sink EDID data pointer is NULL, it will cause an unexpected error. [How] Check data pointer is not NULL first. Reviewed-by: Yihan Zhu <yihan.zhu@amd.com> Signed-off-by: Richard Chiang <Richard.Chiang@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Add frame skip feature support flagChunTao Tso
[WHY] The set_replay_frame_skip_number() function should not execute when the link does not support the Frame Skipping feature. [HOW] Add a new field `frame_skip_supported` to struct replay_config to indicate whether the link supports frame skipping. Check this flag at the beginning of set_replay_frame_skip_number() and return early if the feature is not supported. Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: ChunTao Tso <chuntao.tso@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/pm: force send pcie parmater on navi1xYang Wang
v1: the PMFW didn't initialize the PCIe DPM parameters and requires the KMD to actively provide these parameters. v2: clean & remove unused code logic (lijo) Fixes: 1a18607c07bb ("drm/amd/pm: override pcie dpm parameters only if it is necessary") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4671 Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: use dma_fence_get_status() for adapter resetAlex Deucher
We need to check if the fence was signaled without an error as the per queue resets may have signalled the fence while attempting to reset the queue. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05Documentation/amdgpu: Add UMA carveout detailsYo-Jung Leo Lin (AMD)
Add documentation for the uma/carveout_options and uma/carveout attributes in sysfs Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add UMA allocation interfaces to sysfsYo-Jung Leo Lin (AMD)
Add a uma/ directory containing two sysfs files as interfaces to inspect or change UMA carveout size. These files are: - uma/carveout_options: a read-only file listing all the available UMA allocation options and their index. - uma/carveout: a file that is both readable and writable. On read, it shows the index of the current setting. Writing a valid index into this file allows users to change the UMA carveout size to that option on the next boot. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add UMA allocation setting helpersYo-Jung Leo Lin (AMD)
On some platforms, UMA allocation size can be set using the ATCS methods. Add helper functions to interact with this functionality. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add helper to read UMA carveout infoYo-Jung Leo Lin (AMD)
Currently, the available UMA allocation configs in the integrated system information table have not been parsed. Add a helper function to retrieve and store these configs. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: parse UMA size-getting/setting bits in ATCS maskYo-Jung Leo Lin (AMD)
The capabilities of getting and setting VRAM carveout size are exposed in the ATCS mask. Parse and store these capabilities for future use. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: always backup and reemit fencesAlex Deucher
If when we backup the ring contents for reemit before a ring reset, we skip jobs associated with the bad context, however, we need to make sure the fences are reemited as unprocessed submissions may depend on them. v2: clean up fence handling, make helpers static Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: don't reemit ring contents more than onceAlex Deucher
If we cancel a bad job and reemit the ring contents, and we get another timeout, cancel everything rather than reemitting. The wptr markers are only relevant for the original emit. If we reemit, the wptr markers are no longer correct. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add helpers to access cross-die registers smn addr for soc v1_0Le Ma
Encode die_id/socket_id for upper 32bits of soc v1_0 registers SMN address. v2: fix logical error caught by clang Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: RLC-G VF Register Access InterfaceBokun Zhang
- Implement Gfx v12.1 VFi interface under SRIOV - Redirect all RLCG interface access to new function after Gfx v12.1 v2: squash in register updates Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: set aid_mask for soc v1Likun Gao
Set aid_mask via xcc_mask. v2: squash in follow up change Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Enable support for PSP 15_0_0Pratik Vishwakarma
Add support for PSP v 15.0.0. Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add MP 15.0.0 headersAlex Deucher
Add headers for MP 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add queue reset support for jpeg 5.3Alex Deucher
Enable queue reset for JPEG 5.3. Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu/discovery: add vcn and jpeg ip blockSaleemkhan Jamadar
Add VCN and jpeg IPs v5_3_0 blocks. Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu/jpeg: Add jpeg 5.3.0 supportSaleemkhan Jamadar
Add the Jpeg IP v5_3_0 code base. Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add VCN 5.3.0 headersAlex Deucher
Add headers for VCN 5.3.0. v2: Squash in updates (Alex) Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: reserve umf hole size at vram high end for gfx v12.1Le Ma
This region is reserved by firmware thus carve it out in driver. v2: set reserve size based on aid configuration. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Use explicit VCN instance 0 in SR-IOV initSrinivasan Shanmugam
vcn_v2_0_start_sriov() declares a local variable "i" initialized to zero and uses it only as the instance index in SOC15_REG_OFFSET(UVD, i, ...). The value is never changed and all other fields are taken from adev->vcn.inst[0], so this path only ever programs VCN instance 0. This triggered a Smatch: warn: iterator 'i' not incremented Replace the dummy iterator with an explicit instance index of 0 in SOC15_REG_OFFSET() calls. Fixes: dd26858a9cd8 ("drm/amdgpu: implement initialization part on VCN2.0 for SRIOV") Reported by: Dan Carpenter <dan.carpenter@linaro.org> Cc: darlington Opara <darlington.opara@amd.com> Cc: Jinage Zhao <jiange.zhao@amd.com> Cc: Monk Liu <Monk.Liu@amd.com> Cc: Emily Deng <Emily.Deng@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: enable CP interrupt for gfx v12_1 in frontdoor loading caseLe Ma
Enable cp interrupt for event detection since GFX CGCG and LS has been enabled by firmware. v2: enable CP INT by merely checking fw_load_type Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Apply VGPR bank state fixup on gfx12.1 trap exitJay Cornwall
- Identify co-issue of S_SET_VGPR_MSB and VALU with banked VGPR - Restore previous bank setting when exiting the trap v2: - Refine VOP3PX2 detection - Improve load pipelining - Fix a comment typo Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Joseph Greathouse <joseph.greathouse@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Fix VGPR bank state save in gfx12.1 trap handlerJay Cornwall
S_SETREG_IMM32_B32 does not apply a mask to the MODE bank bits. SRC2 is consequently unconditonally cleared during context save. Use S_SETREG_B32 instead to preserve SRC2. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Add sysfs up clean for gfx_v12_1Asad Kamal
Add sysfs clean up for gfx_v12_1 during gfx fini sequence. This will prevent following crash while reloading driver 2645.490824] R13: 000055d0cb186330 R14: 000055d0cb185ed0 R15: 000055d0cb188f40 [ 2645.490825] </TASK> [ 2645.490836] amdgpu 0000:02:00.0: amdgpu: failed to create xcp sysfs files [ 2645.490937] amdgpu 0000:02:00.0: amdgpu: sw_init of IP block <gfx_v12_1> failed -17 [ 2645.491018] amdgpu 0000:02:00.0: amdgpu: amdgpu_device_ip_init failed [ 2645.491098] amdgpu 0000:02:00.0: amdgpu: Fatal error during GPU init [ 2645.491547] amdgpu 0000:02:00.0: amdgpu: amdgpu: finishing device. [ 2648.549939] ------------[ cut here ]------------ [ 2648.549942] WARNING: CPU: 0 PID: 2459 at /tmp/amd.aIpOeG3c/amd/amdgpu/amdgpu_irq.c: Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Add metadata ring buffer for computeDavid Yat Sin
Add support for separate ring-buffer for metadata packets when using compute queues. Userspace application allocate the metadata ring-buffer and the queue ring-buffer with a single allocation. The metadata ring-buffer starts after the queue ring-buffer. Signed-off-by: David Yat Sin <David.YatSin@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12_1Shaoyun Liu
Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Update TCP Control register on GFX 12.1Mukul Joshi
Update TCP CNTL register to disable some features not supported on GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Add back CWSR trap handler for GFX 12.1Mukul Joshi
CWSR Trap handler for GFX 12.1 was missed when merging changes from 6.14 NPI branch to 6.16 NPI branch. This change adds back the CWSR trap handler for GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Cleanup gmc_v12_1 after 6.16 mergeMukul Joshi
After the 6.16 merge, some changes not applicable to GFX 12.1 were added in the gmc_v12_1_get_vm_pte function. Additionally, add the case for MTYPE RW for GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Disable TCP Early Write Ack for GFX 12.1Mukul Joshi
Disable the TCP Early Write Ack feature on GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: enable precise memory operations for gfx1250Jonathan Kim
Enable precise memory for GFX 1250. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: fix partitioned gfx12 address watch enablementJonathan Kim
GFX 12 devices that support spatial partitioning should use the WREG32 per XCC macro when updating address watch settings, similar to GFX 9 devices that support spatial partitioning. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Implement CU Masking for GFX 12.1Mukul Joshi
Add CU masking implementation for GFX 12.1. Add a local implementation for GFX 12.1 instead of using the generic function defined in kfd_mqd_manager.c because of some quirks in the way CU mask is handled on GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: skip gfxhub tlb flush if gfx is power offLikun Gao
Skip for gfxhub tlb flush for gc v12_1 if gfx is not poweron. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Add gfx_v12_1_kfd2kgd interface for GFX12_1Likun Gao
Create new kfd2kgd interface for gfx v12_1, based on gfx v12. Support register program accoding to xcc id. V2: Fix SDMA register address for muti-xcc. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: update mcm_addr_lut data for imu v12_1Likun Gao
Support for partition mode to program MCM_ADDR_LUT. v2: clean up (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Init mcm_addr look up tableHawking Zhang
Encode mcm address look up table in SPX mode as a temp solution. v2: fill in when interface is ready (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Always set PTE.B for device memory on GFX 12.1Mukul Joshi
On GFX 12.1, we need to set the atomics bit (PTE.B) always for device memory. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu/gfx12.1: Don't fetch default register values from hardware in mqd ↵Lang Yu
init 1. We can't assure the fetched values are always default register values. Observing non-zero cp_hqd_pq_rptr in mes_v12_1_self_test->init_mqd() where no GRBM_GFX_CNTL is specified. 2. See commit fc3c139cf043 ("drm/amdgpu/gfx12: don't read registers in mqd init"). Signed-off-by: Lang Yu <lang.yu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd: Convert DRM_*() to drm_*()Mario Limonciello (AMD)
The drm_*() macros include the device which is helpful for debugging issues in multi-GPU systems. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd: Drop amdgpu prefix from message printsMario Limonciello (AMD)
Hardcoding the prefix isn't necessary when using drm_* or dev_* message prints. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd: Convert amdgpu_display from DRM_* to drm_ macrosMario Limonciello (AMD)
drm_* macros show the device they were called with which is helpful in multi-GPU systems. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Fix DPMS log printingMario Limonciello (AMD)
[Why] Spaces before newline are not necessary. Inserting newlines in multi-line strings are harder to follow when tracing messages. [How] Drop extra new lines and split multi-line messages into one print per line. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd: Drop dev_fmt prefixMario Limonciello (AMD)
The `amdgpu:` prefix in dev_fmt() isn't needed because the core already includes the driver in the print. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd: Pass `adev` to amdgpu_gfx_parse_disable_cu()Mario Limonciello (AMD)
In order for messages to be attribute to the correct device amdgpu_gfx_parse_disable_cu() needs to know what device is being operated on. Pass the argument in. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd: Add correct prefix for VBIOS messageMario Limonciello (AMD)
It's not obvious which GPU the ATOM BIOS message goes with. Use drm_info() to show the correct one. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Correct the topology message for APUsMario Limonciello (AMD)
At bootup on a Strix machine the following message comes up: ``` amdgpu: Topology: Add dGPU node [0x150e:0x1002] ``` This is an APU though. Clarify the messaging by only offer a "CPU node" or "GPU node" message. Also set the message as VID:DID instead which is how other messages work. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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