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path: root/drivers/gpu/drm/amd/amdgpu
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2020-01-16drm/amdgpu: export function to flush TLB via pasidAlex Sierra
This can be used directly from amdgpu and amdkfd to invalidate TLB through pasid. It supports gmc v7, v8, v9 and v10. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amdgpu: replace kcq enable/disable functions on gfx_v9Alex Sierra
[Why] There are HW-indpendent functions that enables and disables kcq. These functions use the kiq_pm4_funcs implementation. [How] Local kcq enable and disable functions removed and replace it by the generic kcq enable under amdgpu_gfx Signed-off-by: Alex Sierra <alex.sierra@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amdgpu: implement tlbs invalidate on gfx9 gfx10Alex Sierra
tlbs invalidate pointer function added to kiq_pm4_funcs struct. This way, tlb flush can be done through kiq member. TLBs invalidatation implemented for gfx9 and gfx10. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amdgpu: kiq pm4 function implementation for gfx_v9Alex Sierra
Functions implemented from kiq_pm4_funcs struct members for gfx_v9 version. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/amdgpu: Avoid reclaim fs while eviction lockAlex Sierra
[Why] Avoid reclaim filesystem while eviction lock is held called from MMU notifier. [How] Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked. Using memalloc_nofs_save / memalloc_nofs_restore API. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-16drm/ttm: nuke invalidate_caches callbackChristian König
Another completely unused feature. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Link: https://patchwork.freedesktop.org/patch/348265/
2020-01-15drm/amdgpu: update goldensetting for renoirAaron Liu
Update mmSDMA0_UTCL1_WATERMK golden setting for renoir. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu/debugfs: properly handle runtime pmAlex Deucher
If driver debugfs files are accessed, power up the GPU when necessary. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu/pm: properly handle runtime pmAlex Deucher
If power management sysfs or debugfs files are accessed, power up the GPU when necessary. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: add header file for macro SZ_1MFlora Cui
Fixes: 4dee6e4ca50a ("drm/amdgpu: use linux size macro to simplify ONE_Kib & One_Mib") Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu/psp: declare navi1x ta firmwareAlex Deucher
So that it gets included in the initrd. At the moment this is optional firmware that contains support for HDCP. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: Match TC hash settings to DF settings (v2)Joseph Greathouse
On Arcturus, data fabric hashing is set by the VBIOS, and affects which addresses map to which memory channels. The gfx core's caches also need to know this mapping, but the hash settings for these these caches is set by the driver. This change queries the DF to understand how the VBIOS configured DF, then matches the TC hash configuration bits to do the same thing. v2: squash in warning fix Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: Create generic DF struct in adevJoseph Greathouse
The only data fabric information the adev struct currently contains is a function pointer table. In the near future, we will be adding some cached DF information into adev. As such, this patch creates a new amdgpu_df struct for adev. Right now, it only containst the old function pointer table, but new stuff will be added soon. Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: preserve RSMU UMC index mode stateJohn Clements
between UMC RAS err register access restore previous RSMU UMC index mode state Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: disable XGMI TA unload for arcturusJohn Clements
in event of GPU reset, XGMI TA unload causes unrecoverable GPU hang Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: update goldensetting for renoirAaron Liu
Update mmSDMA0_UTCL1_WATERMK golden setting for renoir. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu/gmc10: free stolen memory in late_initAlex Deucher
We don't need to store the pre-OS console memory after the driver has loaded so free it. Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu/gmc10: remove dead codeAlex Deucher
Leftover from bring up. We look up the actual pre-OS memory usage value later in the same function. Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: enable S/G display on PCO and RV2 (v2)Alex Deucher
It should work on all Raven variants, but some users have reported issues with original Raven with IOMMU enabled. So far there have been no issues observed with PCO or RV2. v2: split out the dm init and domain changes into separate patches. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu/gfx9: remove unused sdma headersAlex Deucher
All of the sdma stuff these were used for moves to the sdma code, so remove them. Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: check sdma ras funcs pointer before accessingHawking Zhang
sdma ras funcs are not supported by ASIC prior to vega20 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: calculate MCUMC_ADDRT0 per asic's UMC offsetGuchun Chen
Hardcoded offset is not friendly. And another benifit of this patch is to keep read and write access to this register be consistent with other similar UMC regsiters in this file. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu/sriov: workaround on rev_id for Navi12 under sriovTiecheng Zhou
guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, as a consequence, the rev_id and external_rev_id are wrong. workaround it by hardcoding the rev_id to 0, which is the default value. v2. add comment in the code Signed-off-by: Tiecheng Zhou <Tiecheng.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: read sdma edc counter to clear the countersHawking Zhang
SDMA edc counter registers were added in gfx edc counters array. When querying gfx error counter in that array, there is no way to differentiate sdma instance number for different asic and then results to NULL pointer access when trying to read sdma register base address for instances greater than 2 on Vega20. In addition, this also results to wrong gfx error counters since it actually added sdma edc counters. Therefore, sdma edc counter registers should be separated from gfx edc counter regsiter array and only get initialized when driver tries to enable sdma ras. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: add ras_late_init and ras_fini for sdma v4Hawking Zhang
move ras_late_init and ras_fini to sdma_ras_funcs table Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: support error reporting for sdma ip blockHawking Zhang
invoke sdma query_ras_error_count to get sdma single bit error count Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: add query_ras_error_count function for sdma v4Hawking Zhang
query_ras_error_count function will be invoked to query single bit error count detected in sdma ip block Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: enable VCN2.5 IP block for ArcturusLeo Liu
With default PSP FW loading Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu/vcn2.5: fix PSP FW loading for the second instanceLeo Liu
ucodes for instances are from different location Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdgpu: catch amdgpu_irq_add_id failureNirmoy Das
Do not ignore amdgpu_irq_add_id return value while registering VMC page fault interrupt. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amd/powerplay: cover the powerplay implementation details V3Evan Quan
This can save users much troubles. As they do not actually need to care whether swSMU or traditional powerplay routine should be used. V2: apply the fixes to vi.c and cik.c also V3: squash in oops fix Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-14drm/amdkfd: Improve function get_sdma_rlc_reg_offset() (v2)Yong Zhao
The SOC15_REG_OFFSET() macro needs to dereference adev->reg_offset[IP] pointer, which is sometimes NULL when there are fewer than 8 sdma engines. Avoid that by not initializing the array regardless. v2: squash in warning fixes Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07Revert "drm/amdgpu: Set no-retry as default."Alex Deucher
This reverts commit 51bfac71cade386966791a8db87a5912781d249f. This causes stability issues on some raven boards. Revert for now until a proper fix is completed. Bug: https://gitlab.freedesktop.org/drm/amd/issues/934 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206017 Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu/gfx: simplify old firmware warningAlex Deucher
Put it on one line to avoid whitespace issues when printing in the log. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu/gmc10: use common invalidation engine helperAlex Deucher
Rather than open coding it. This also changes the free masks to better reflect the usage by other components. Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu/gmc: move invaliation bitmap setup to common codeAlex Deucher
So it can be shared with newer GMC versions. Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu: updated UMC error address record with correct channel indexJohn Clements
defined macros for repetitive for loops Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu: resolved bug in UMC RAS CE queryJohn Clements
switch CE counter register access' to use SMN disable UMC indexing mode Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amd/powerplay: cleanup the interfaces for powergate setting through SMUEvan Quan
Provided an unified entry point. And fixed the confusing that the API usage is conflict with what the naming implies. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amd/amdgpu: L1 Policy(5/5) - removed IH_CHICKEN from VFZhigang Luo
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amd/amdgpu: L1 Policy(3/5) - removed ECC interrupt from VFZhigang Luo
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amd/amdgpu: L1 Policy(2/5) - removed GC GRBM violations from gfxhubZhigang Luo
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amd/amdgpu: L1 Policy(1/5) - removed VM settings for mmhub and gfxhub ↵Zhigang Luo
from VF Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu: removed GFX RAS support check in UMC ECC callbackJohn Clements
enable GPU recovery in event of uncorrectable UMC error Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu: added function to wait for PSP BL availabilityJohn Clements
reduced duplicate code increased wait time for PSP BL readiness Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu: use linux size macro to simplify ONE_Kib & One_MibKevin Wang
replace internal size macro with linux size macro Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu: resolve bug in UMC 6 error counter queryJohn Clements
iterate over all error counter registers in SMN space removed support error counter access via MMIO Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07amd/amdgpu/sriov tdr enablement with pp_onevf_modeJack Zhang
Under sriov and pp_onevf mode, 1.take resume instead of hw_init for smc recover to avoid potential memory leak. 2.add return condition inside smc resume function for sriov_pp_onevf_mode and pm_enabled param. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07amd/amdgpu/sriov enable onevf mode for ARCTURUS VFJack Zhang
Before, initialization of smu ip block would be skipped for sriov ASICs. But if there's only one VF being used, guest driver should be able to dump some HW info such as clks, temperature,etc. To solve this, now after onevf mode is enabled, host driver will notify guest. If it's onevf mode, guest will do smu hw_init and skip some steps in normal smu hw_init flow because host driver has already done it for smu. With this fix, guest app can talk with smu and dump hw information from smu. v2: refine the logic for pm_enabled.Skip hw_init by not changing pm_enabled. v3: refine is_support_sw_smu and fix some indentation issue. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-01-07drm/amdgpu: update UMC 6.1 RAS error counter register access pathJohn Clements
use proper method for SMN register access Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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