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2025-09-01arm64: dts: qcom: msm8953: add spi_7Barnabás Czémán
Add spi_7 can be found in MSM8953 devices. Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20250830-msm8953-spi-fix-v1-3-89950eaf10fe@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01arm64: dts: qcom: msm8953: correct SPI pinctrlsBarnabás Czémán
SPI pinctrls should handle 4 pins MOSI, MISO, CLK and CS. This change adding the missing pins for pinctrls and correcting CS pins according to downstream sources. Fixes: be69109e93c78 ("arm64: dts: qcom: msm8953: add SPI interfaces") Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20250830-msm8953-spi-fix-v1-2-89950eaf10fe@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01arm64: dts: qcom: msm8953: fix SPI clocksBarnabás Czémán
Fix SPI clocks, accidentally I2C clocks was assigned for SPI interfaces. Fixes: be69109e93c78 ("arm64: dts: qcom: msm8953: add SPI interfaces") Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20250830-msm8953-spi-fix-v1-1-89950eaf10fe@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01arm64: dts: qcom: sdm845-shift-axolotl: set chassis typeGuido Günther
It's a handset. Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/3e04efc06a795a32b0080b2f23a138e139057b02.1756569434.git.agx@sigxcpu.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01arm64: dts: qcom: sm8650: Additionally manage MXC power domain in camccJagadeesh Kona
Camcc requires both MMCX and MXC rails to be powered ON to configure the camera PLLs on SM8650 platform. Hence add MXC power domain to camcc node on SM8650. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-6-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camccVladimir Zapolskiy
Camcc requires both MMCX and MXC rails to be powered ON to configure the camera PLLs on SM8550 platform. Hence add MXC power domain to camcc node on SM8550. Fixes: e271b59e39a6f ("arm64: dts: qcom: sm8550: Add camera clock controller") Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-5-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01arm64: dts: qcom: sm8450: Additionally manage MXC power domain in camccJagadeesh Kona
Camcc requires both MMCX and MXC rails to be powered ON to configure the camera PLLs on SM8450 platform. Hence add MXC power domain to camcc node on SM8450. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-4-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01arm64: dts: qcom: sm8650: Additionally manage MXC power domain in videoccJagadeesh Kona
Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8650 platform. Hence add MXC power domain to videocc node on SM8650. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-3-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01arm64: dts: qcom: sm8550: Additionally manage MXC power domain in videoccJagadeesh Kona
Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8550 platform. Hence add MXC power domain to videocc node on SM8550. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-2-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01arm64: dts: qcom: sm8450: Additionally manage MXC power domain in videoccJagadeesh Kona
Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8450 platform. Hence add MXC power domain to videocc node on SM8450. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-1-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01ARM: dts: qcom: Use GIC_SPI for interrupt-map for readabilityKrzysztof Kozlowski
Decoding interrupt-map is tricky, because it consists of five components. Use known GIC_SPI define in final interrupt specifier component makes easier to read. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-15-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01ARM: dts: qcom: sdx55: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: qcom-sdx55.dtsi:343.4-346.30: Warning (interrupt_map): /soc/pcie@1c00000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@17800000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-14-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01ARM: dts: qcom: ipq8064: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: qcom-ipq8064.dtsi:1201.4-1204.29: Warning (interrupt_map): /soc/pcie@1b900000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@2000000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-13-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01ARM: dts: qcom: apq8064: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: qcom-apq8064.dtsi:1353.4-1356.29: Warning (interrupt_map): /soc/pcie@1b500000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@2000000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-12-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01ARM: dts: qcom: ipq4019: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: qcom-ipq4019.dtsi:431.4-434.30: Warning (interrupt_map): /soc/pcie@40000000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@b000000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-11-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-09-01nios2: implement architecture-specific portion of sys_clone3Simon Schuster
This commit adds the sys_clone3 entry point for nios2. An architecture-specific wrapper (__sys_clone3) is required to save and restore additional registers to the kernel stack via SAVE_SWITCH_STACK and RESTORE_SWITCH_STACK. Signed-off-by: Simon Schuster <schuster.simon@siemens-energy.com> Link: https://lore.kernel.org/20250901-nios2-implement-clone3-v2-4-53fcf5577d57@siemens-energy.com Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-09-01arch: copy_thread: pass clone_flags as u64Simon Schuster
With the introduction of clone3 in commit 7f192e3cd316 ("fork: add clone3") the effective bit width of clone_flags on all architectures was increased from 32-bit to 64-bit, with a new type of u64 for the flags. However, for most consumers of clone_flags the interface was not changed from the previous type of unsigned long. While this works fine as long as none of the new 64-bit flag bits (CLONE_CLEAR_SIGHAND and CLONE_INTO_CGROUP) are evaluated, this is still undesirable in terms of the principle of least surprise. Thus, this commit fixes all relevant interfaces of the copy_thread function that is called from copy_process to consistently pass clone_flags as u64, so that no truncation to 32-bit integers occurs on 32-bit architectures. Signed-off-by: Simon Schuster <schuster.simon@siemens-energy.com> Link: https://lore.kernel.org/20250901-nios2-implement-clone3-v2-3-53fcf5577d57@siemens-energy.com Fixes: c5febea0956fd387 ("fork: Pass struct kernel_clone_args into copy_thread") Acked-by: Guo Ren (Alibaba Damo Academy) <guoren@kernel.org> Acked-by: Andreas Larsson <andreas@gaisler.com> # sparc Acked-by: David Hildenbrand <david@redhat.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> # m68k Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-09-01ARM: s3c6400_defconfig: Drop MTD_NAND_S3C2410Krzysztof Kozlowski
MTD_NAND_S3C2410 driver was removed from the kernel, so cleanup defconfig as well. Link: https://lore.kernel.org/r/20250830-s3c-cleanup-nand-v1-4-05b99ef990fe@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-09-01x86/sev: Indicate the SEV-SNP guest supports Secure AVICNeeraj Upadhyay
Now that Secure AVIC support is complete, make it part of to the SNP present features. Co-developed-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828113225.209174-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/sev: Prevent SECURE_AVIC_CONTROL MSR interception for Secure AVIC guestsNeeraj Upadhyay
The SECURE_AVIC_CONTROL MSR holds the GPA of the guest APIC backing page and bitfields to control enablement of Secure AVIC and whether the guest allows NMIs to be injected by the hypervisor. This MSR is populated by the guest and can be read by the guest to get the GPA of the APIC backing page. The MSR can only be accessed in Secure AVIC mode. Any attempt to access it when not in Secure AVIC mode results in #GP. So, the hypervisor should not intercept it. A #VC exception will be generated otherwise. If this occurs and Secure AVIC is enabled, terminate the guest execution. Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828113119.209135-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/apic: Enable Secure AVIC in the control MSRNeeraj Upadhyay
With all the pieces in place now, enable Secure AVIC in the Secure AVIC Control MSR. Any access to x2APIC MSRs are emulated by the hypervisor before Secure AVIC is enabled in the control MSR. Post Secure AVIC enablement, all x2APIC MSR accesses (whether accelerated by AVIC hardware or trapped as a #VC exception) operate on the vCPU's APIC backing page. Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828112126.209028-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/apic: Add kexec support for Secure AVICNeeraj Upadhyay
Add a apic->teardown() callback to disable Secure AVIC before rebooting into the new kernel. This ensures that the new kernel does not access the old APIC backing page which was allocated by the previous kernel. Such accesses can happen if there are any APIC accesses done during the guest boot before Secure AVIC driver probe is done by the new kernel (as Secure AVIC would have remained enabled in the Secure AVIC control MSR). Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/20250828112008.209013-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/apic: Handle EOI writes for Secure AVIC guestsNeeraj Upadhyay
Secure AVIC accelerates the guest's EOI MSR writes for edge-triggered interrupts. For level-triggered interrupts, EOI MSR writes trigger a #VC exception with an SVM_EXIT_AVIC_UNACCELERATED_ACCESS error code. To complete EOI handling, the #VC exception handler would need to trigger a GHCB protocol MSR write event to notify the hypervisor about completion of the level-triggered interrupt. Hypervisor notification is required for cases like emulated IO-APIC, to complete and clear interrupt in the IO-APIC's interrupt state. However, #VC exception handling adds extra performance overhead for APIC register writes. In addition, for Secure AVIC, some unaccelerated APIC register MSR writes are trapped, whereas others are faulted. This results in additional complexity in #VC exception handling for unaccelerated APIC MSR accesses. So, directly do a GHCB protocol based APIC EOI MSR write from apic->eoi() callback for level-triggered interrupts. Use WRMSR for edge-triggered interrupts, so that hardware re-evaluates any pending interrupt which can be delivered to the guest vCPU. For level-triggered interrupts, re-evaluation happens on return from VMGEXIT corresponding to the GHCB event for APIC EOI MSR write. Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828111654.208987-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/apic: Read and write LVT* APIC registers from HV for SAVIC guestsNeeraj Upadhyay
The Hypervisor needs information about the current state of the LVT registers for device emulation and NMIs. So, forward reads and write of these registers to the hypervisor for Secure AVIC enabled guests. Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828111356.208972-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/sev: Enable NMI support for Secure AVICKishon Vijay Abraham I
Now that support to send NMI IPI and support to inject NMI from the hypervisor has been added, set V_NMI_ENABLE in the VINTR_CTRL field of the VMSA to enable NMI for Secure AVIC guests. [ bp: Zap useless brackets. ] Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828111315.208959-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/apic: Allow NMI to be injected from hypervisor for Secure AVICNeeraj Upadhyay
Secure AVIC requires the "AllowedNmi" bit in the Secure AVIC Control MSR to be set for an NMI to be injected from the hypervisor. So set it. Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828111243.208946-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/apic: Add support to send NMI IPI for Secure AVICNeeraj Upadhyay
Secure AVIC introduces a new field in the APIC backing page "NmiReq" that has to be set by the guest to request a NMI IPI through APIC_ICR write. Add support to set NmiReq appropriately to send NMI IPI. Co-developed-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828111213.208933-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/sev: Initialize VGIF for secondary vCPUs for Secure AVICKishon Vijay Abraham I
Virtual GIF (VGIF) provides masking capability for when virtual interrupts (virtual maskable interrupts, virtual NMIs) can be taken by the guest vCPU. The Secure AVIC hardware reads VGIF state from the vCPU's VMSA. So, set VGIF for secondary CPUs (the configuration for the boot CPU is done by the hypervisor), to unmask delivery of virtual interrupts to the vCPU. Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828111141.208920-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/apic: Support LAPIC timer for Secure AVICNeeraj Upadhyay
Secure AVIC requires the LAPIC timer to be emulated by the hypervisor. KVM already supports emulating the LAPIC timer using hrtimers. In order to emulate it, APIC_LVTT, APIC_TMICT and APIC_TDCR register values need to be propagated to the hypervisor for arming the timer. APIC_TMCCT register value has to be read from the hypervisor, which is required for calibrating the APIC timer. So, read/write all APIC timer registers from/to the hypervisor. Co-developed-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828110926.208866-1-Neeraj.Upadhyay@amd.com
2025-09-01x86/apic: Add support to send IPI for Secure AVICNeeraj Upadhyay
Secure AVIC hardware accelerates only Self-IPI, i.e. on WRMSR to APIC_SELF_IPI and APIC_ICR (with destination shorthand equal to Self) registers, hardware takes care of updating the APIC_IRR in the APIC backing page of the vCPU. For other IPI types (cross-vCPU, broadcast IPIs), software needs to take care of updating the APIC_IRR state of the target vCPUs and to ensure that the target vCPUs notice the new pending interrupt. Add new callbacks in the Secure AVIC driver for sending IPI requests. These callbacks update the IRR in the target guest vCPU's APIC backing page. To ensure that the remote vCPU notices the new pending interrupt, reuse the GHCB MSR handling code in vc_handle_msr() to issue APIC_ICR MSR-write GHCB protocol event to the hypervisor. For Secure AVIC guests, on APIC_ICR write MSR exits, the hypervisor notifies the target vCPU by either sending an AVIC doorbell (if target vCPU is running) or by waking up the non-running target vCPU. Co-developed-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828110824.208851-1-Neeraj.Upadhyay@amd.com
2025-09-01arm64: dts: rockchip: fix USB on RADXA ROCK 5TNicolas Frattaroli
The RADXA ROCK 5T board uses the same GPIO pin for controlling the USB host port regulator. This control pin was mistakenly left out of the ROCK 5T device tree. Reported-by: FUKAUMI Naoki <naoki@radxa.com> Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38609886; Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree") Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250825-rock5t-usb-fix-v1-1-de71954a1bb5@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-09-01x86/apic: Add an update_vector() callback for Secure AVICNeeraj Upadhyay
Add an update_vector() callback to set/clear the ALLOWED_IRR field in a vCPU's APIC backing page for vectors which are emulated by the hypervisor. The ALLOWED_IRR field indicates the interrupt vectors which the guest allows the hypervisor to inject (typically for emulated devices). Interrupt vectors used exclusively by the guest itself and the vectors which are not emulated by the hypervisor, such as IPI vectors, should not be set by the guest in the ALLOWED_IRR fields. As clearing/setting state of a vector will also be used in subsequent commits for other APIC registers (such as APIC_IRR update for sending IPI), add a common update_vector() in the Secure AVIC driver. [ bp: Massage commit message. ] Co-developed-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828110255.208779-4-Neeraj.Upadhyay@amd.com
2025-09-01fs: add an icount_read helperJosef Bacik
Instead of doing direct access to ->i_count, add a helper to handle this. This will make it easier to convert i_count to a refcount later. Signed-off-by: Josef Bacik <josef@toxicpanda.com> Link: https://lore.kernel.org/9bc62a84c6b9d6337781203f60837bd98fbc4a96.1756222464.git.josef@toxicpanda.com Signed-off-by: Christian Brauner <brauner@kernel.org>
2025-09-01x86/apic: Add update_vector() callback for APIC driversNeeraj Upadhyay
Add an update_vector() callback to allow APIC drivers to perform driver specific operations on external vector allocation/teardown on a CPU. This callback will be used by the Secure AVIC APIC driver to configure the vectors which a guest vCPU allows the hypervisor to send to it. As system vectors have fixed vector assignments and are not dynamically allocated, add an apic_update_vector() public API to facilitate update_vector() callback invocation for them. This will be used for Secure AVIC enabled guests to allow the hypervisor to inject system vectors which are emulated by the hypervisor such as APIC timer vector and HYPERVISOR_CALLBACK_VECTOR. While at it, cleanup line break in apic_update_irq_cfg(). Co-developed-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Kishon Vijay Abraham I <kvijayab@amd.com> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/20250828110255.208779-3-Neeraj.Upadhyay@amd.com
2025-09-01x86/apic: Initialize APIC ID for Secure AVICNeeraj Upadhyay
Initialize the APIC ID in the Secure AVIC APIC backing page with the APIC_ID MSR value read from the hypervisor. CPU topology evaluation later during boot would catch and report any duplicate APIC ID for two CPUs. Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Tianyu Lan <tiala@microsoft.com> Link: https://lore.kernel.org/20250828110255.208779-2-Neeraj.Upadhyay@amd.com
2025-09-01Merge tag 'renesas-arm-soc-for-v6.18-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/arm Renesas ARM SoC updates for v6.18 - Use the SZ_256K definition. * tag 'renesas-arm-soc-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: ARM: shmobile: rcar-gen2: Use SZ_256K definition Link: https://lore.kernel.org/r/cover.1756468045.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01ARM: defconfig: pxa: Remove duplicate CONFIG_USB_GPIO_VBUS entryJihed Chaibi
The pxa_defconfig file defines CONFIG_USB_GPIO_VBUS twice, first as built-in ('y') and then as a module ('m'). The kconfig system correctly uses the last definition, but the duplication is confusing. Remove the obsolete configuration to resolve the ambiguity and clean up the configuration. Fixes: 2002f3968714 ("ARM: refresh defconfig files") Signed-off-by: Jihed Chaibi <jihed.chaibi.dev@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'renesas-arm-defconfig-for-v6.18-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig Renesas ARM defconfig updates for v6.18 - Enable support for the Renesas RZ/T2H serial driver and the RZ/V2H(P) RSPI driver in the ARM64 defconfig. * tag 'renesas-arm-defconfig-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: defconfig: Enable the RZ/V2H(P) RSPI driver arm64: defconfig: Enable Renesas RZ/T2H serial SCI Link: https://lore.kernel.org/r/cover.1756468043.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'sti-dt-for-v6.18-round1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into soc/dt STi dt fixes: - Drop STiH407/10-B2120 DT boards and bindings. - Remove remaining STiH415/6 reference from STi machine. - Fix phy-names value for stih407-family.dtsi. * tag 'sti-dt-for-v6.18-round1' of https://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: ARM: sti: drop B2120 board support ARM: sti: removal of stih415/stih416 related entries dt-bindings: arm: sti: drop B2120 board support ARM: dts: sti: rename SATA phy-names Link: https://lore.kernel.org/r/e4703e99-e44e-41d2-b744-a12ed4cb6692@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'renesas-dts-for-v6.18-tag1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.18 - Add initial support for the RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs and their evaluation boards, - Add SPI support for the RZ/V2H SoC, - Add DMAC and I3C support for the RZ/G3E SoC, - Add I3C support for the RZ/G3S SoCs, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (31 commits) arm64: dts: renesas: Minor whitespace cleanup arm64: dts: renesas: sparrow-hawk: Set VDDQ18_25_AVB voltage on EVTB1 arm64: dts: renesas: sparrow-hawk: Invert microSD voltage selector on EVTB1 arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable I2C0 and I2C1 support arm64: dts: renesas: r9a09g077: Add pinctrl node arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5 arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5 arm64: dts: renesas: r9a09g047: Add I3C node arm64: dts: renesas: r9a08g045: Add I3C node arm64: dts: renesas: sparrow-hawk: Update thermal trip points arm64: dts: renesas: rzg2: Increase CANFD clock rates arm64: dts: renesas: rcar-gen3: Increase CANFD clock rates ARM: dts: renesas: porter: Fix CAN pin group ARM: dts: renesas: r7s72100: Add boot phase tags arm64: dts: renesas: sparrow-hawk: Describe generic SPI NOR support arm64: dts: renesas: rzg2lc-smarc: Disable CAN-FD channel0 arm64: dts: renesas: r9a09g047: Add DMAC nodes arm64: dts: renesas: r9a09g057h48-kakip: Fix misplaced article arm64: dts: renesas: r9a09g087: Add SDHI nodes arm64: dts: renesas: r9a09g077: Add SDHI nodes ... Link: https://lore.kernel.org/r/cover.1756468048.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'ixp4xx-dts-v6.18' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt IXP4xx DTS updates for v6.18: Add the Actiontec router MI424WR A/C and D device trees. Prerequisite DT bindings have been merged in networking and GPIO git trees: https://lore.kernel.org/netdev/175106401649.2079310.16035106613106076029.git-patchwork-notify@kernel.org/ https://lore.kernel.org/linux-gpio/175614780274.8817.4717113656972710108.b4-ty@linaro.org/ * tag 'ixp4xx-dts-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: dts: Add ixp4xx Actiontec MI424WR device trees dt-bindings: arm: ixp4xx: List actiontec devices dt-bindings: Add Actiontec vendor prefix Link: https://lore.kernel.org/r/CACRpkdZoDCXgsTGzUUWABbp_r1Xjv7vp7_NjEnEWzMmDQG+UJQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'ux500-dts-v6.18' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into soc/dt Ux500 DTS changes for v6.18 - Fix a GPIO hog name. - Move custom wakeup GPIO to a proper GPIO IRQ line rising edge wakeup. * tag 'ux500-dts-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: ste-ux500-samsung: dts bluetooth wakeup interrupt ARM: dts: st: ste-nomadik: Align GPIO hog name with bindings Link: https://lore.kernel.org/r/CACRpkdaGWVe7TNVz_L=gFh3AfzqnEq4rrOLo8x6gXUORA+MMpw@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'nuvoton-arm64-6.18-devicetree-0' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt Early Nuvoton arm64 devicetree updates for 6.18 Integrate changes from Tomer reworking devicetree pinctrl, reset, and clk nodes for NPCM845-based platforms. * tag 'nuvoton-arm64-6.18-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: arm64: dts: nuvoton: add refclk and update peripheral clocks for NPCM845 arm64: dts: nuvoton: combine NPCM845 reset and clk nodes arm64: dts: nuvoton: npcm845: Add pinctrl groups Link: https://lore.kernel.org/r/bf3734aab62a5fcc8959261551bb4b1fa636efbd.camel@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'nuvoton-arm-6.18-devicetree-0' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt Early Nuvoton ARM devicetree updates for 6.18 So far we have just the one fix from Krzysztof that switches some nodes to use generic names, as recommended by the spec. * tag 'nuvoton-arm-6.18-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: ARM: dts: nuvoton: Use generic "ethernet" as node name Link: https://lore.kernel.org/r/5e7e5d2cedb3bb232420ad720c857b95d8c02f21.camel@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'aspeed-6.18-devicetree-0' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt Early ASPEED devicetree updates for 6.18 Notable changes: - Meta's Wedge400 and Fuji boards have had parallel devicetrees added for a transition to a new static flash layout. The original layout is deprecated and I anticipate removing related devicetrees in future releases. New platforms: - Darwin (Meta) Darwin is Meta's rack switch platform with an AST2600 BMC integrated for health monitoring purpose. Updates and fixes: - GB200NVL (Nvidia): Networking, I2C, regulators, GPIOs - Wedge400, Fuji (Meta): Fix warnings from devicetree bindings - Use fixed-layout for NVMEM on Asrock platforms - Various: minor fixes for warnings from FSI devicetree bindings * tag 'aspeed-6.18-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: (24 commits) ARM: dts: aspeed: x570d4u: convert NVMEM content to layout syntax ARM: dts: aspeed: romed8hm3: convert NVMEM content to layout syntax ARM: dts: aspeed: e3c256d4i: convert NVMEM content to layout syntax ARM: dts: aspeed: e3c246d4i: convert NVMEM content to layout syntax ARM: dts: aspeed: Add missing "ibm,spi-fsi" compatibles ARM: dts: aspeed: Drop "fsi-master" compatibles ARM: dts: aspeed: Drop "no-gpio-delays" ARM: dts: aspeed: Add Facebook Darwin (AST2600) BMC dt-bindings: arm: aspeed: add Facebook Darwin board ARM: dts: aspeed: facebook-fuji: Include facebook-fuji-data64.dts ARM: dts: aspeed: Add Facebook Fuji-data64 (AST2600) Board dt-bindings: arm: aspeed: add Facebook Fuji-data64 board ARM: dts: aspeed: wedge400: Include wedge400-data64.dts ARM: dts: aspeed: Add Facebook Wedge400-data64 (AST2500) BMC dt-bindings: arm: aspeed: add Facebook Wedge400-data64 board ARM: dts: aspeed: Add facebook-bmc-flash-layout-128-data64.dtsi ARM: dts: aspeed: Move eMMC out of ast2600-facebook-netbmc-common.dtsi ARM: dts: aspeed: Fix DTB warnings in ast2600-facebook-netbmc-common.dtsi ARM: dts: aspeed: fuji: Fix DTB warnings ARM: dts: aspeed: wedge400: Fix DTB warnings ... Link: https://lore.kernel.org/r/cb634cffaf0db9d25fb3062f0eee41e03955321f.camel@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'apple-soc-dt-6.18' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt Apple SoC device tree changes for v6.18, part 1 - Added SMC nodes for M1 and M2 including the PMU GPIO controller and reboot sub-nodes. This now allows to reboot these systems and is required to later enable the power GPIO line for the WiFi board. - Added i2c nodes for A7 - A11 SoCs Signed-off-by: Sven Peter <sven@kernel.org> * tag 'apple-soc-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: arm64: dts: apple: t600x: Add SMC node arm64: dts: apple: t8112: Add SMC node arm64: dts: apple: t8103: Add SMC node arm64: dts: apple: t8015: Add I2C nodes arm64: dts: apple: t8011: Add I2C nodes arm64: dts: apple: t8010: Add I2C nodes arm64: dts: apple: s8001: Add I2C nodes arm64: dts: apple: s800-0-3: Add I2C nodes arm64: dts: apple: t7001: Add I2C nodes arm64: dts: apple: t7000: Add I2C nodes arm64: dts: apple: s5l8960x: Add I2C nodes Link: https://lore.kernel.org/r/20250816171501.31944-1-sven@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01arm64: dts: axiado: Add missing UART aliasesHarshit Shah
Axiado AX3000 EVK has total of 4 UART ports. Add missing alias for uart0, uart1, uart2. This fixes the probe failures on the remaining UARTs. Fixes: 1f7055779001 ("arm64: dts: axiado: Add initial support for AX3000 SoC and eval board") Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Harshit Shah <hshah@axiado.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01Merge tag 'imx-fixes-6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 6.17: - Correct FlexCAN PHY settings on imx95-19x19-evk board (Haibo Chen) - Add missing microSD slot supplies for DH electronics i.MX8M Plus boards (Marek Vasut) - Fix assigned clocks for JPEG encoder node on i.MX95 (Marek Vasut) - A couple of regulator setting fixes for imx8mp-tqma8mpql board (Markus Niebel) * tag 'imx-fixes-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx95: Fix JPEG encoder node assigned clock arm64: dts: imx95-19x19-evk: correct the phy setting for flexcan1/2 arm64: dts: imx8mp: Fix missing microSD slot vqmmc on Data Modul i.MX8M Plus eDM SBC arm64: dts: imx8mp: Fix missing microSD slot vqmmc on DH electronics i.MX8M Plus DHCOM arm64: dts: imx8mp-tqma8mpql: remove virtual 3.3V regulator arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off Link: https://lore.kernel.org/r/aK6BuzIYwUBRU1GW@dragon Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-01xtensa: simdisk: add input size check in proc_write_simdiskMiaoqian Lin
A malicious user could pass an arbitrarily bad value to memdup_user_nul(), potentially causing kernel crash. This follows the same pattern as commit ee76746387f6 ("netdevsim: prevent bad user input in nsim_dev_health_break_write()") Fixes: b6c7e873daf7 ("xtensa: ISS: add host file-based simulated disk") Fixes: 16e5c1fc3604 ("convert a bunch of open-coded instances of memdup_user_nul()") Cc: stable@vger.kernel.org Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Message-Id: <20250829083015.1992751-1-linmq006@gmail.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2025-09-01kbuild: Add missing $(objtree) prefix to powerpc crtsavres.o artifactKienan Stewart
In the upstream commit 214c0eea43b2ea66bcd6467ea57e47ce8874191b ("kbuild: add $(objtree)/ prefix to some in-kernel build artifacts") artifacts required for building out-of-tree kernel modules had $(objtree) prepended to them to prepare for building in other directories. When building external modules for powerpc, arch/powerpc/lib/crtsavres.o is required for certain configurations. This artifact is missing the prepended $(objtree). Fixes: 13b25489b6f8 ("kbuild: change working directory to external module directory with M=") Acked-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Nicolas Schier <n.schier@avm.de> Tested-by: Nicolas Schier <n.schier@avm.de> Signed-off-by: Kienan Stewart <kstewart@efficios.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20250218-buildfix-extmod-powerpc-v2-1-1e78fcf12b56@efficios.com
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