summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2025-12-19arm64: dts: broadcom: rp1: drop RP1 overlayAndrea della Porta
RP1 support loaded from overlay has been dropped from the driver and the DTB intended to be loaded with the overlay no longer exists. Drop unused include file and overlay. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/85167b815d41ed9ed690ad239a19de5cd2e8be1c.1766077285.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-12-19arm64: dts: broadcom: bcm2712: fix RP1 endpoint PCI topologyAndrea della Porta
The node describing the RP1 endpoint currently uses a specific name ('rp1_nexus') that does not correctly reflect the PCI topology. Update the DT with the correct topology and use generic node names. Additionally, since the driver dropped overlay support in favor of a fully described DT, rename '...-ovl-rp1.dts' to '...-base.dtsi' for inclusion in the board DTB, as it is no longer compiled as a standalone DTB. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/827b12ba48bb47bc77a0f5e5617aea961c8bc6b5.1766077285.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-12-19arm64: dts: mediatek: Apply mt8395-radxa DT overlay at build timeRob Herring (Arm)
It's a requirement that DT overlays be applied at build time in order to validate them as overlays are not validated on their own. Add missing target for mt8395-radxa hd panel overlay. Fixes: 4c8ff61199a7 ("arm64: dts: mediatek: mt8395-radxa-nio-12l: Add Radxa 8 HD panel") Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: AngeloGioacchino Del Regno <angelogiaocchino.delregno@collabora.com> Link: https://patch.msgid.link/20251205215940.19287-1-linux@fw-web.de Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-19arm64: dts: mediatek: mt7988: add dtbs with applied overlays for bpi-r4 (pro)Frank Wunderlich
Build devicetree binaries for testing overlays and providing users full dtb without using overlays for Bananapi R4 (pro) variants. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://patch.msgid.link/20251119175124.48947-3-linux@fw-web.de Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-19arm64: dts: mediatek: mt7986: add dtbs with applied overlays for bpi-r3Frank Wunderlich
Build devicetree binaries for testing overlays and providing users full dtb without using overlays. Suggested-by: Rob Herring <robh+dt@kernel.org> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Fixes: a58c36806741 ("arm64: dts: mediatek: mt7988a-bpi-r4pro: Add mmc overlays") Fixes: dec929e61a42 ("arm64: dts: mediatek: mt7988a-bpi-r4-pro: Add PCIe overlays") Fixes: 714a80ced07a ("arm64: dts: mediatek: mt7988a-bpi-r4: Add dt overlays for sd + emmc") Fixes: 312189ebb802 ("arm64: dts: mt7986: add overlay for SATA power socket on BPI-R3") Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251119175124.48947-2-linux@fw-web.de Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-12-19riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V JupiterJavier Martinez Canillas
Define the SpacemiT P1 PMIC voltage regulators and their constraints. The power management hardware design on the Milk-V Jupiter is identical to the Banana Pi BPI-F3, so the DT Nodes were taken from k1-bananapi-f3.dts. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251206134532.1741648-4-javierm@redhat.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-12-19riscv: dts: spacemit: Define fixed regulators for Milk-V JupiterJavier Martinez Canillas
Define the DC power input and the 4v power as fixed regulator supplies. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251206134532.1741648-3-javierm@redhat.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-12-19riscv: dts: spacemit: Enable i2c8 adapter for Milk-V JupiterJavier Martinez Canillas
The adapter is used to access the SpacemiT P1 PMIC present in this board. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251206134532.1741648-2-javierm@redhat.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-12-19perf: Use EXPORT_SYMBOL_FOR_KVM() for the mediated APIsPeter Zijlstra
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20251208115156.GE3707891@noisy.programming.kicks-ass.net
2025-12-19riscv: Add SBI debug trigger extension and function idsHimanshu Chauhan
Debug trigger extension is an SBI extension to support native debugging in S-mode and VS-mode. This patch adds the extension and the function IDs defined by the extension. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Link: https://patch.msgid.link/20250710125231.653967-2-hchauhan@ventanamicro.com [pjw@kernel.org: updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-19riscv/atomic.h: use RISCV_FULL_BARRIER in _arch_atomic* function.Zongmin Zhou
Replace the same code with the pre-defined macro RISCV_FULL_BARRIER to simplify the code. Signed-off-by: Zongmin Zhou <zhouzongmin@kylinos.cn> Link: https://patch.msgid.link/20251120095831.64211-1-min_halo@163.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-19riscv: hwprobe: export Zilsd and Zclsd ISA extensionsPincheng Wang
Export Zilsd and Zclsd ISA extensions through hwprobe. Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Link: https://patch.msgid.link/20250826162939.1494021-4-pincheng.plct@isrc.iscas.ac.cn [pjw@kernel.org: fixed whitespace; updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-19riscv: add ISA extension parsing for Zilsd and ZclsdPincheng Wang
Add parsing for Zilsd and Zclsd ISA extensions which were ratified in commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Link: https://patch.msgid.link/20250826162939.1494021-3-pincheng.plct@isrc.iscas.ac.cn [pjw@kernel.org: cleaned up checkpatch issues, whitespace; updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-19riscv: mm: use xchg() on non-atomic_long_t variables, not atomic_long_xchg()Paul Walmsley
Let's not call atomic_long_xchg() on something that's not an atomic_long_t, and just use xchg() instead. Continues the cleanup from commit 546e42c8c6d94 ("riscv: Use an atomic xchg in pudp_huge_get_and_clear()"), Cc: Alexandre Ghiti <alex@ghiti.fr> Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-19riscv: mm: ptep_get_and_clear(): avoid atomic ops when !CONFIG_SMPPaul Walmsley
When !CONFIG_SMP, there's no need for atomic operations in ptep_get_and_clear(), so, similar to x86, let's not use atomics in this case. Cc: Alexandre Ghiti <alex@ghiti.fr> Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-19riscv: mm: pmdp_huge_get_and_clear(): avoid atomic ops when !CONFIG_SMPPaul Walmsley
When !CONFIG_SMP, there's no need for atomic operations in pmdp_huge_get_and_clear(), so, similar to what x86 does, let's not use atomics in this case. See also commit 546e42c8c6d94 ("riscv: Use an atomic xchg in pudp_huge_get_and_clear()"). Cc: Alexandre Ghiti <alex@ghiti.fr> Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-19riscv: signal: abstract header saving for setup_sigcontextAndy Chiu
The function save_v_state() served two purposes. First, it saved extension context into the signal stack. Then, it constructed the extension header if there was no fault. The second part is independent of the extension itself. As a result, we can pull that part out, so future extensions may reuse it. This patch adds arch_ext_list and makes setup_sigcontext() go through all possible extensions' save() callback. The callback returns a positive value indicating the size of the successfully saved extension. Then the kernel proceeds to construct the header for that extension. The kernel skips an extension if it does not exist, or if the saving fails for some reasons. The error code is propagated out on the later case. This patch does not introduce any functional changes. Signed-off-by: Andy Chiu <andybnac@gmail.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-16-b55691eacf4f@rivosinc.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-18x86/irq_remapping: Sanitize posted_msi_supported()Thomas Gleixner
posted_msi_supported() is a misnomer as it actually checks whether it is enabled or not. Aside of that this does not take CONFIG_X86_POSTED_MSI into account which is required to actually use it. Rename it to posted_msi_enabled() and make the return value depend on CONFIG_X86_POSTED_MSI, which allows the compiler to eliminate the related dead code and data if disabled: text data bss dec hex filename 10046 701 3296 14043 36db drivers/iommu/intel/irq_remapping.o 9904 413 3296 13613 352d drivers/iommu/intel/irq_remapping.o Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20251125214631.170499997@linutronix.de
2025-12-18x86/irq: Cleanup posted MSI codeThomas Gleixner
Make code and comments readable and use __this_cpu..() as this is guaranteed to be invoked with interrupts disabled. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20251125214631.108458942@linutronix.de
2025-12-19Merge tag 'libcrypto-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux Pull crypto library fixes from Eric Biggers: - Fix a performance issue with the scoped_ksimd() macro (new in 6.19) where it unnecessarily initialized the entire fpsimd state. - Add a missing gitignore entry for a generated file added in 6.18. * tag 'libcrypto-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux: lib/crypto: riscv: Add poly1305-core.S to .gitignore arm64/simd: Avoid pointless clearing of FP/SIMD buffer
2025-12-18Merge tag 'kvm-x86-fixes-6.19-rc1' of https://github.com/kvm-x86/linux into HEADPaolo Bonzini
KVM fixes for 6.19-rc1 - Add a missing "break" to fix param parsing in the rseq selftest. - Apply runtime updates to the _current_ CPUID when userspace is setting CPUID, e.g. as part of vCPU hotplug, to fix a false positive and to avoid dropping the pending update. - Disallow toggling KVM_MEM_GUEST_MEMFD on an existing memslot, as it's not supported by KVM and leads to a use-after-free due to KVM failing to unbind the memslot from the previously-associated guest_memfd instance. - Harden against similar KVM_MEM_GUEST_MEMFD goofs, and prepare for supporting flags-only changes on KVM_MEM_GUEST_MEMFD memlslots, e.g. for dirty logging. - Set exit_code[63:32] to -1 (all 0xffs) when synthesizing a nested SVM_EXIT_ERR (a.k.a. VMEXIT_INVALID) #VMEXIT, as VMEXIT_INVALID is defined as -1ull (a 64-bit value). - Update SVI when activating APICv to fix a bug where a post-activation EOI for an in-service IRQ would effective be lost due to SVI being stale. - Immediately refresh APICv controls (if necessary) on a nested VM-Exit instead of deferring the update via KVM_REQ_APICV_UPDATE, as the request is effectively ignored because KVM thinks the vCPU already has the correct APICv settings.
2025-12-18arm64: defconfig: enable clocks, interconnect and pinctrl for Qualcomm KaanapaliJingyi Wang
Enable necessary drivers for booting Qualcomm Kaanapali QRD and MTP boards. The serial engine must be properly setup before kernel reach "init", so UART driver and its dependencies needs to be built in, enable its dependency GCC, interconnect and pinctrl as built-in meanwhile enable TCSRCC as module. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251215-knp-dts-v4-2-1541bebeb89f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-18arm64: dts: qcom: kaanapali: Add base QRD boardJingyi Wang
Add initial support for Qualcomm Kaanapali QRD board which enables SD Card, UFS and booting to shell with UART console. Written with help from Jishnu Prakash (added RPMhPD nodes), Nitin Rawat (added ufs) and Manish Pandey (added SD Card). Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251215-knp-dts-v4-5-1541bebeb89f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-18arm64: dts: qcom: kaanapali: Add base MTP boardJingyi Wang
Add initial support for Qualcomm Kaanapali MTP board which enables PCIe, SD Card, UFS and booting to shell with UART console. Written with help from Jishnu Prakash (added RPMhPD nodes), Nitin Rawat (added UFS), Manish Pandey (added SD Card) and Qiang Yu (added PCIe). Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251215-knp-dts-v4-4-1541bebeb89f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-18arm64: dts: qcom: Introduce Kaanapali SoCJingyi Wang
Kaanapali is Snapdragon SoC from Qualcomm. Features added in this patch: - CPUs with PSCI idle states and cpufreq - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect with CPU BWMONs - QuP with UART - SMMU - RPMhPD - UFS with Inline Crypto Engine - LLCC - Watchdog - SD Card - PCIe Written with help from Raviteja Laggyshetty (added interconnect nodes), Taniya Das (added Clock Controllers and cpufreq), Jishnu Prakash (added RPMhPD), Nitin Rawat (added UFS), Gaurav Kashyap (added ICE), Manish Pandey (added SD Card) and Qiang Yu (added PCIe). Co-developed-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com> Signed-off-by: Tengfei Fan <tengfei.fan@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251215-knp-dts-v4-3-1541bebeb89f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-18x86/bug: Fix old GCC compile failsPeter Zijlstra
For some mysterious reasons the GCC 8 and 9 preprocessor manages to sporadically fumble _ASM_BYTES(0x0f, 0x0b): $ grep ".byte[ ]*0x0f" defconfig-build/drivers/net/wireless/realtek/rtlwifi/base.s 1: .byte0x0f,0x0b ; 1: .byte 0x0f,0x0b ; which makes the assembler upset and all that. While there are more _ASM_BYTES() users (notably the NOP instructions), those don't seem affected. Therefore replace the offending ASM_UD2 with one using the ud2 mnemonic. Reported-by: Jean Delvare <jdelvare@suse.de> Suggested-by: Uros Bizjak <ubizjak@gmail.com> Fixes: 85a2d4a890dc ("x86,ibt: Use UDB instead of 0xEA") Cc: stable@kernel.org Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20251218104659.GT3911114@noisy.programming.kicks-ass.net
2025-12-17arm64: dts: qcom: glymur: Add header file for IPCC physical client IDsSibi Sankar
Physical client IDs are used on Glymur Inter Process Communication Controller (IPCC), add a corresponding header file. Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-3-62ffb4168dff@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-17arm64: dts: qcom: kaanapali: Add header file for IPCC physical client IDsJingyi Wang
On earlier platforms, Inter Process Communication Controller (IPCC) used virtual client IDs and performed virtual-to-physical mapping in hardware, so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across platforms. Physical client IDs instead of virtual client IDs are used for qcom new platforms like Kaanapali, which will be parsed by the devicetree and passed to hardware to use Physical client IDs directly. Since physical client IDs could vary across platforms, add a corresponding header file for the Kaanapali platform. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-2-62ffb4168dff@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-12-17x86/msi: Make irq_retrigger() functional for posted MSIThomas Gleixner
Luigi reported that retriggering a posted MSI interrupt does not work correctly. The reason is that the retrigger happens at the vector domain by sending an IPI to the actual vector on the target CPU. That works correctly exactly once because the posted MSI interrupt chip does not issue an EOI as that's only required for the posted MSI notification vector itself. As a consequence the vector becomes stale in the ISR, which not only affects this vector but also any lower priority vector in the affected APIC because the ISR bit is not cleared. Luigi proposed to set the vector in the remap PIR bitmap and raise the posted MSI notification vector. That works, but that still does not cure a related problem: If there is ever a stray interrupt on such a vector, then the related APIC ISR bit becomes stale due to the lack of EOI as described above. Unlikely to happen, but if it happens it's not debuggable at all. So instead of playing games with the PIR, this can be actually solved for both cases by: 1) Keeping track of the posted interrupt vector handler state 2) Implementing a posted MSI specific irq_ack() callback which checks that state. If the posted vector handler is inactive it issues an EOI, otherwise it delegates that to the posted handler. This is correct versus affinity changes and concurrent events on the posted vector as the actual handler invocation is serialized through the interrupt descriptor lock. Fixes: ed1e48ea4370 ("iommu/vt-d: Enable posted mode for device MSIs") Reported-by: Luigi Rizzo <lrizzo@google.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Luigi Rizzo <lrizzo@google.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20251125214631.044440658@linutronix.de Closes: https://lore.kernel.org/lkml/20251124104836.3685533-1-lrizzo@google.com
2025-12-17perf/x86/cstate: Add Airmont NPMartin Schiller
From the perspective of Intel cstate residency counters, the Airmont NP (aka Lightning Mountain) is identical to the Airmont. Signed-off-by: Martin Schiller <ms@dev.tdt.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20251124074846.9653-4-ms@dev.tdt.de
2025-12-17perf/x86/intel: Add Airmont NPMartin Schiller
The Intel / MaxLinear Airmont NP (aka Lightning Mountain) supports the same architectual and non-architecural events as Airmont. Signed-off-by: Martin Schiller <ms@dev.tdt.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20251124074846.9653-3-ms@dev.tdt.de
2025-12-17perf/x86/msr: Add Airmont NPMartin Schiller
Like Airmont, the Airmont NP (aka Intel / MaxLinear Lightning Mountain) supports SMI_COUNT MSR. Signed-off-by: Martin Schiller <ms@dev.tdt.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Link: https://patch.msgid.link/20251124074846.9653-2-ms@dev.tdt.de
2025-12-17x86/unwind_user: Simplify unwind_user_word_size()Jens Remus
Get rid of superfluous ifdef and return explicit word size depending on 32-bit or 64-bit mode. Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Jens Remus <jremus@linux.ibm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20251208160352.1363040-5-jremus@linux.ibm.com
2025-12-17x86/unwind_user: Guard unwind_user_word_size() by UNWIND_USERJens Remus
The unwind user framework in general requires an architecture-specific implementation of unwind_user_word_size() to be present for any unwind method, whether that is fp or a future other method, such as potentially sframe. Guard unwind_user_word_size() by the availability of the UNWIND_USER framework instead of the specific HAVE_UNWIND_USER_FP method. This facilitates to selectively disable HAVE_UNWIND_USER_FP on x86 (e.g. for test purposes) once a new unwind method is added to unwind user. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20251208160352.1363040-4-jremus@linux.ibm.com
2025-12-17unwind_user/fp: Use dummies instead of ifdefJens Remus
This simplifies the code. unwind_user_next_fp() does not need to return -EINVAL if config option HAVE_UNWIND_USER_FP is disabled, as unwind_user_start() will then not select this unwind method and unwind_user_next() will therefore not call it. Provide (1) a dummy definition of ARCH_INIT_USER_FP_FRAME, if the unwind user method HAVE_UNWIND_USER_FP is not enabled, (2) a common fallback definition of unwind_user_at_function_start() which returns false, and (3) a common dummy definition of ARCH_INIT_USER_FP_ENTRY_FRAME. Note that enabling the config option HAVE_UNWIND_USER_FP without defining ARCH_INIT_USER_FP_FRAME triggers a compile error, which is helpful when implementing support for this unwind user method in an architecture. Enabling the config option when providing an arch- specific unwind_user_at_function_start() definition makes it necessary to also provide an arch-specific ARCH_INIT_USER_FP_ENTRY_FRAME definition. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20251208160352.1363040-3-jremus@linux.ibm.com
2025-12-17perf/x86/amd: Support PERF_PMU_CAP_MEDIATED_VPMU for AMD hostSandipan Das
Apply the PERF_PMU_CAP_MEDIATED_VPMU flag for version 2 and later implementations of the core PMU. Aside from having Global Control and Status registers, virtualizing the PMU using the mediated model requires an interface to set or clear the overflow bits in the Global Status MSRs while restoring or saving the PMU context of a vCPU. PerfMonV2-capable hardware has additional MSRs for this purpose, namely PerfCntrGlobalStatusSet and PerfCntrGlobalStatusClr, thereby making it suitable for use with mediated vPMU. Signed-off-by: Sandipan Das <sandipan.das@amd.com> Signed-off-by: Mingwei Zhang <mizhang@google.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Xudong Hao <xudong.hao@intel.com> Link: https://patch.msgid.link/20251206001720.468579-14-seanjc@google.com
2025-12-17perf/x86/intel: Support PERF_PMU_CAP_MEDIATED_VPMUKan Liang
Apply the PERF_PMU_CAP_MEDIATED_VPMU for Intel core PMU. It only indicates that the perf side of core PMU is ready to support the mediated vPMU. Besides the capability, the hypervisor, a.k.a. KVM, still needs to check the PMU version and other PMU features/capabilities to decide whether to enable support mediated vPMUs. [sean: massage changelog] Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Mingwei Zhang <mizhang@google.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Xudong Hao <xudong.hao@intel.com> Link: https://patch.msgid.link/20251206001720.468579-13-seanjc@google.com
2025-12-17perf/x86/core: Plumb mediated PMU capability from x86_pmu to x86_pmu_capMingwei Zhang
Plumb mediated PMU capability to x86_pmu_cap in order to let any kernel entity such as KVM know that host PMU support mediated PMU mode and has the implementation. Signed-off-by: Mingwei Zhang <mizhang@google.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Xudong Hao <xudong.hao@intel.com> Link: https://patch.msgid.link/20251206001720.468579-12-seanjc@google.com
2025-12-17perf/x86/core: Do not set bit width for unavailable countersSandipan Das
Not all x86 processors have fixed counters. It may also be the case that a processor has only fixed counters and no general-purpose counters. Set the bit widths corresponding to each counter type only if such counters are available. Fixes: b3d9468a8bd2 ("perf, x86: Expose perf capability to other modules") Signed-off-by: Sandipan Das <sandipan.das@amd.com> Co-developed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Mingwei Zhang <mizhang@google.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Xudong Hao <xudong.hao@intel.com> Link: https://patch.msgid.link/20251206001720.468579-11-seanjc@google.com
2025-12-17perf/x86/core: Add APIs to switch to/from mediated PMI vector (for KVM)Sean Christopherson
Add APIs (exported only for KVM) to switch PMIs to the dedicated mediated PMU IRQ vector when loading guest context, and back to perf's standard NMI when the guest context is put. I.e. route PMIs to PERF_GUEST_MEDIATED_PMI_VECTOR when the guest context is active, and to NMIs while the host context is active. While running with guest context loaded, ignore all NMIs (in perf). Any NMI that arrives while the LVTPC points at the mediated PMU IRQ vector can't possibly be due to a host perf event. Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20251206001720.468579-10-seanjc@google.com
2025-12-17perf/x86/core: Register a new vector for handling mediated guest PMIsSean Christopherson
Wire up system vector 0xf5 for handling PMIs (i.e. interrupts delivered through the LVTPC) while running KVM guests with a mediated PMU. Perf currently delivers all PMIs as NMIs, e.g. so that events that trigger while IRQs are disabled aren't delayed and generate useless records, but due to the multiplexing of NMIs throughout the system, correctly identifying NMIs for a mediated PMU is practically infeasible. To (greatly) simplify identifying guest mediated PMU PMIs, perf will switch the CPU's LVTPC between PERF_GUEST_MEDIATED_PMI_VECTOR and NMI when guest PMU context is loaded/put. I.e. PMIs that are generated by the CPU while the guest is active will be identified purely based on the IRQ vector. Route the vector through perf, e.g. as opposed to letting KVM attach a handler directly a la posted interrupt notification vectors, as perf owns the LVTPC and thus is the rightful owner of PERF_GUEST_MEDIATED_PMI_VECTOR. Functionally, having KVM directly own the vector would be fine (both KVM and perf will be completely aware of when a mediated PMU is active), but would lead to an undesirable split in ownership: perf would be responsible for installing the vector, but not handling the resulting IRQs. Add a new perf_guest_info_callbacks hook (and static call) to allow KVM to register its handler with perf when running guests with mediated PMUs. Note, because KVM always runs guests with host IRQs enabled, there is no danger of a PMI being delayed from the guest's perspective due to using a regular IRQ instead of an NMI. Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Xudong Hao <xudong.hao@intel.com> Link: https://patch.msgid.link/20251206001720.468579-9-seanjc@google.com
2025-12-17perf: Add APIs to create/release mediated guest vPMUsKan Liang
Currently, exposing PMU capabilities to a KVM guest is done by emulating guest PMCs via host perf events, i.e. by having KVM be "just" another user of perf. As a result, the guest and host are effectively competing for resources, and emulating guest accesses to vPMU resources requires expensive actions (expensive relative to the native instruction). The overhead and resource competition results in degraded guest performance and ultimately very poor vPMU accuracy. To address the issues with the perf-emulated vPMU, introduce a "mediated vPMU", where the data plane (PMCs and enable/disable knobs) is exposed directly to the guest, but the control plane (event selectors and access to fixed counters) is managed by KVM (via MSR interceptions). To allow host perf usage of the PMU to (partially) co-exist with KVM/guest usage of the PMU, KVM and perf will coordinate to a world switch between host perf context and guest vPMU context near VM-Enter/VM-Exit. Add two exported APIs, perf_{create,release}_mediated_pmu(), to allow KVM to create and release a mediated PMU instance (per VM). Because host perf context will be deactivated while the guest is running, mediated PMU usage will be mutually exclusive with perf analysis of the guest, i.e. perf events that do NOT exclude the guest will not behave as expected. To avoid silent failure of !exclude_guest perf events, disallow creating a mediated PMU if there are active !exclude_guest events, and on the perf side, disallowing creating new !exclude_guest perf events while there is at least one active mediated PMU. Exempt PMU resources that do not support mediated PMU usage, i.e. that are outside the scope/view of KVM's vPMU and will not be swapped out while the guest is running. Guard mediated PMU with a new kconfig to help readers identify code paths that are unique to mediated PMU support, and to allow for adding arch- specific hooks without stubs. KVM x86 is expected to be the only KVM architecture to support a mediated PMU in the near future (e.g. arm64 is trending toward a partitioned PMU implementation), and KVM x86 will select PERF_GUEST_MEDIATED_PMU unconditionally, i.e. won't need stubs. Immediately select PERF_GUEST_MEDIATED_PMU when KVM x86 is enabled so that all paths are compile tested. Full KVM support is on its way... [sean: add kconfig and WARNing, rewrite changelog, swizzle patch ordering] Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Mingwei Zhang <mizhang@google.com> Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Xudong Hao <xudong.hao@intel.com> Link: https://patch.msgid.link/20251206001720.468579-5-seanjc@google.com
2025-12-17arm64: dts: nuvoton: npcm845: Minor whitespace cleanupKrzysztof Kozlowski
The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250819131725.86770-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-17ARM: dts: aspeed: bletchley: Fix ADC vref property namesCosmo Chou
Replace non-functional 'vref' with 'aspeed,int-vref-microvolt' using the default 2.5V that the driver was already applying. Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-12-17ARM: dts: aspeed: bletchley: Remove unused i2c13 propertyCosmo Chou
Remove 'aspeed,hw-timeout-ms' property which is not supported by the driver and causes dt-schema warnings. Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-12-17ARM: dts: aspeed: bletchley: Remove unused pca9539 propertiesCosmo Chou
Remove unused #address-cells and #size-cells properties from pca9539 nodes to fix dt-schema warnings. Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-12-17ARM: dts: aspeed: bletchley: Fix SPI GPIO property namesCosmo Chou
Update SPI GPIO properties to use "-gpios" suffix: - gpio-sck -> sck-gpios - gpio-mosi -> mosi-gpios - gpio-miso -> miso-gpios Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-12-17ARM: dts: aspeed: bletchley: Use generic node namesCosmo Chou
Use generic node names to fix dt-schema warnings: - spi1_gpio: rename to generic "spi" node name - LED nodes: rename to led-N and move names to label properties - GPIO key nodes: add "-switch" suffix to node names Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-12-17Merge tag 'bpf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpfLinus Torvalds
Pull bpf fixes from Alexei Starovoitov: - Fix BPF builds due to -fms-extensions. selftests (Alexei Starovoitov), bpftool (Quentin Monnet). - Fix build of net/smc when CONFIG_BPF_SYSCALL=y, but CONFIG_BPF_JIT=n (Geert Uytterhoeven) - Fix livepatch/BPF interaction and support reliable unwinding through BPF stack frames (Josh Poimboeuf) - Do not audit capability check in arm64 JIT (Ondrej Mosnacek) - Fix truncated dmabuf BPF iterator reads (T.J. Mercier) - Fix verifier assumptions of bpf_d_path's output buffer (Shuran Liu) - Fix warnings in libbpf when built with -Wdiscarded-qualifiers under C23 (Mikhail Gavrilov) * tag 'bpf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf: selftests/bpf: add regression test for bpf_d_path() bpf: Fix verifier assumptions of bpf_d_path's output buffer selftests/bpf: Add test for truncated dmabuf_iter reads bpf: Fix truncated dmabuf iterator reads x86/unwind/orc: Support reliable unwinding through BPF stack frames bpf: Add bpf_has_frame_pointer() bpf, arm64: Do not audit capability check in do_jit() libbpf: Fix -Wdiscarded-qualifiers under C23 bpftool: Fix build warnings due to MS extensions net: smc: SMC_HS_CTRL_BPF should depend on BPF_JIT selftests/bpf: Add -fms-extensions to bpf build flags
2025-12-16arm64: dts: qcom: Add dts for Medion SPRCHRGD 14 S1Georg Gottleuber
Initial support for the Medion SPRCHRGD 14 S1, which is based on the Qualcomm Snapdragon X Elite SoC (X1E78100). Working: * Touchpad * Keyboard * eDP * NVMe * USB Type-C port * USB-C DP altmode * HDMI-A port * WiFi * Bluetooth * GPU * Video decoding * USB Type-A * Audio, speakers, microphones - 4x speakers. - 2x dmic - headset * Camera * Fingerprint reader Co-developed-by: Srinivas Kandagatla <srini@kernel.org> Signed-off-by: Srinivas Kandagatla <srini@kernel.org> Co-developed-by: Ettore Chimenti <ettore.chimenti@linaro.org> Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org> Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204155212.230058-6-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-08-20 18:47:13 +0000