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2025-09-15Merge tag 'samsung-dt-6.18' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM changes for v6.18 1. Drop S3C2416 SoC from bindings, because it was removed from kernel in 2023. 2. Add Ethernet attached via SROM controller (memory bus) on SMDK5250. This wasn't tested, but code should work just like it is working on Exynos5410-based boards. * tag 'samsung-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: samsung: smdk5250: add sromc node ARM: dts: samsung: exynos5250: describe sromc bank memory map ARM: dts: samsung: exynos5410: use multiple tuples for sromc ranges dt-bindings: arm: samsung: Drop S3C2416 Link: https://lore.kernel.org/r/20250909184559.105777-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'samsung-dt64-6.18' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.18 1. Exynos850 e850 board: Enable Ethernet. 2. Exynos990: Enable watchdog and USB, add more clock controllers. 3. Exynos2200: Switch to 32-bit address space for blocks, because all peripherals fit there. Add remaining serial engine (USI) nodes (serial, I2C). 4. New Artpec ARTPEC-8 SoC with board. That's a design from Samsung, sharing all basic blocks with other Samsung SoCs (busses, clock controllers, pin controllers, PCIe, USB) and having media/video related blocks from Axis. Only basic support is added here: few clock controllers, pin controller and UART. 5. Several cleanups. * tag 'samsung-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos990: Enable PERIC0 and PERIC1 clock controllers arm64: dts: axis: Add ARTPEC-8 Grizzly dts support arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support dt-bindings: arm: axis: Add ARTPEC-8 grizzly board arm64: dts: exynos8895: Minor whitespace cleanup dt-bindings: arm: Convert Axis board/soc bindings to json-schema arm64: dts: exynos2200: Add default GIC address cells arm64: dts: fsd: Add default GIC address cells arm64: dts: google: gs101: Add default GIC address cells arm64: dts: exynos5433: Add default GIC address cells arm64: dts: exynos2200: define all usi nodes arm64: dts: exynos2200: increase the size of all syscons arm64: dts: exynos2200: use 32-bit address space for /soc arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label arm64: dts: exynos990-r8s: Enable USB arm64: dts: exynos990-c1s: Enable USB arm64: dts: exynos990-x1s-common: Enable USB arm64: dts: exynos990: Add USB nodes arm64: dts: exynos990: Enable watchdog timer arm64: dts: exynos: Add Ethernet node for E850-96 board Link: https://lore.kernel.org/r/20250909180127.99783-4-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Merge tag 'v6.18-rockchip-dts64-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards: FriendlyElec NanoPi Zero2, ArmSoM Sige1, Radxa ROCK 2A/2F, HINLINK H66K / H68K . Interesting new peripherals: I guess the most interesting one is likely the NPU on RK3588. The rocket driver has been merged into both the DRM tree as well as mainline Mesa. Other stll interesting ones are DW-Displayport on RK3588, DSI on RK3576 (missing soc pwm-support to be useful on most boards), thermal support and watchdog on RK3576. The rest peripheral additions on a number of boards (Beelink A1, Pine{phone,book}, rk3576-evb1-v10, Rock 5*, ...) * tag 'v6.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (46 commits) arm64: dts: rockchip: Enable DP2HDMI for ROCK 5 ITX arm64: dts: rockchip: Enable DisplayPort for rk3588s Cool Pi 4B arm64: dts: rockchip: Add DP1 for rk3588 arm64: dts: rockchip: Add DP0 for rk3588 arm64: dts: rockchip: Add FriendlyElec NanoPi Zero2 dt-bindings: arm: rockchip: Add FriendlyElec NanoPi Zero2 arm64: dts: rockchip: Add ArmSoM Sige1 dt-bindings: arm: rockchip: Add ArmSoM Sige1 arm64: dts: rockchip: Add Radxa ROCK 2A/2F dt-bindings: arm: rockchip: Add Radxa ROCK 2A/2F dt-bindings: soc: rockchip: add missing clock reference for rk3576-dcphy syscon arm64: dts: rockchip: add USB3 on Beelink A1 arm64: dts: rockchip: add SPDIF audio to Beelink A1 arm64: dts: rockchip: add IR receiver to rk3328-roc arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro arm64: dts: rockchip: Further describe the WiFi for the Pinebook Pro arm64: dts: rockchip: Enable the NPU on NanoPi R6C/R6S arm64: dts: rockchip: enable NPU on OPI5/5B arm64: dts: rockchip: Add Bluetooth on rk3576-evb1-v10 arm64: dts: rockchip: Add WiFi on rk3576-evb1-v10 ... Link: https://lore.kernel.org/r/5241735.C4sosBPzcN@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15Input: add INPUT_PROP_HAPTIC_TOUCHPADAngela Czubak
INPUT_PROP_HAPTIC_TOUCHPAD property is to be set for a device with simple haptic capabilities. Signed-off-by: Angela Czubak <aczubak@google.com> Co-developed-by: Jonathan Denose <jdenose@google.com> Signed-off-by: Jonathan Denose <jdenose@google.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Benjamin Tissoires <bentiss@kernel.org>
2025-09-15dt-bindings: display: samsung,exynos7-decon: document iommus, memory-region, ↵Kaustabh Chakraborty
and ports Similar to FIMD and Exynos5433's DECON, the Exynos7 DECON hardware: - May optionally require an IOMMU to initialize a display region. - Outputs image data to another block, say an MIC or a DSI master. If an IOMMU is present, it may also require to access the reserved framebuffer region. Document these bindings in the devicetree schema. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15dt-bindings: samsung,mipi-dsim: document exynos7870 DSIM compatibleKaustabh Chakraborty
Add compatible string for Exynos7870 DSIM bridge controller. The device requires four clock sources, in schema they're named as "bus", "pll", "byte", and "esc". Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2025-09-15fs/resctrl: Introduce the interface to switch between monitor modesBabu Moger
Resctrl subsystem can support two monitoring modes, "mbm_event" or "default". In mbm_event mode, monitoring event can only accumulate data while it is backed by a hardware counter. In "default" mode, resctrl assumes there is a hardware counter for each event within every CTRL_MON and MON group. Introduce mbm_assign_mode resctrl file to switch between mbm_event and default modes. Example: To list the MBM monitor modes supported: $ cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_event] default To enable the "mbm_event" counter assignment mode: $ echo "mbm_event" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode To enable the "default" monitoring mode: $ echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode Reset MBM event counters automatically as part of changing the mode. Clear both architectural and non-architectural event states to prevent overflow conditions during the next event read. Clear assignable counter configuration on all the domains. Also, enable auto assignment when switching to "mbm_event" mode. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Introduce the interface to modify assignments in a groupBabu Moger
Enable the mbm_l3_assignments resctrl file to be used to modify counter assignments of CTRL_MON and MON groups when the "mbm_event" counter assignment mode is enabled. Process the assignment modifications in the following format: <Event>:<Domain id>=<Assignment state>;<Domain id>=<Assignment state> Event: A valid MBM event in the /sys/fs/resctrl/info/L3_MON/event_configs directory. Domain ID: A valid domain ID. When writing, '*' applies the changes to all domains. Assignment states: _ : Unassign a counter. e : Assign a counter exclusively. Examples: $ cd /sys/fs/resctrl $ cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=e To unassign the counter associated with the mbm_total_bytes event on domain 0: $ echo "mbm_total_bytes:0=_" > mbm_L3_assignments $ cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=e mbm_local_bytes:0=e;1=e To unassign the counter associated with the mbm_total_bytes event on all the domains: $ echo "mbm_total_bytes:*=_" > mbm_L3_assignments $ cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=_;1=_ mbm_local_bytes:0=e;1=e Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Introduce mbm_L3_assignments to list assignments in a groupBabu Moger
Introduce the mbm_L3_assignments resctrl file associated with CTRL_MON and MON resource groups to display the counter assignment states of the resource group when "mbm_event" counter assignment mode is enabled. Display the list in the following format: <Event>:<Domain id>=<Assignment state>;<Domain id>=<Assignment state> Event: A valid MBM event listed in /sys/fs/resctrl/info/L3_MON/event_configs directory. Domain ID: A valid domain ID. The assignment state can be one of the following: _ : No counter assigned. e : Counter assigned exclusively. Example: To list the assignment states for the default group $ cd /sys/fs/resctrl $ cat /sys/fs/resctrl/mbm_L3_assignments mbm_total_bytes:0=e;1=e mbm_local_bytes:0=e;1=e Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Introduce mbm_assign_on_mkdir to enable assignments on mkdirBabu Moger
The "mbm_event" counter assignment mode allows users to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as it is assigned. Introduce a user-configurable option that determines if a counter will automatically be assigned to an RMID, event pair when its associated monitor group is created via mkdir. Accessible when "mbm_event" counter assignment mode is enabled. Suggested-by: Peter Newman <peternewman@google.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Provide interface to update the event configurationsBabu Moger
When "mbm_event" counter assignment mode is enabled, users can modify the event configuration by writing to the 'event_filter' resctrl file. The event configurations for mbm_event mode are located in /sys/fs/resctrl/info/L3_MON/event_configs/. Update the assignments of all CTRL_MON and MON resource groups when the event configuration is modified. Example: $ mount -t resctrl resctrl /sys/fs/resctrl $ cd /sys/fs/resctrl/ $ cat info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memory $ echo "local_reads,local_non_temporal_writes" > info/L3_MON/event_configs/mbm_total_bytes/event_filter $ cat info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,local_non_temporal_writes Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Add event configuration directory under info/L3_MON/Babu Moger
The "mbm_event" counter assignment mode allows the user to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as it is assigned. The user can specify the memory transaction(s) for the counter to track. When this mode is supported, the /sys/fs/resctrl/info/L3_MON/event_configs directory contains a sub-directory for each MBM event that can be assigned to a counter. The MBM event sub-directory contains a file named "event_filter" that is used to view and modify which memory transactions the MBM event is configured with. Create /sys/fs/resctrl/info/L3_MON/event_configs directory on resctrl mount and pre-populate it with directories for the two existing MBM events: mbm_total_bytes and mbm_local_bytes. Create the "event_filter" file within each MBM event directory with the needed *show() that displays the memory transactions with which the MBM event is configured. Example: $ mount -t resctrl resctrl /sys/fs/resctrl $ cd /sys/fs/resctrl/ $ cat info/L3_MON/event_configs/mbm_total_bytes/event_filter local_reads,remote_reads,local_non_temporal_writes, remote_non_temporal_writes,local_reads_slow_memory, remote_reads_slow_memory,dirty_victim_writes_all $ cat info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memory Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Support counter read/reset with mbm_event assignment modeBabu Moger
When "mbm_event" counter assignment mode is enabled, the architecture requires a counter ID to read the event data. Introduce an is_mbm_cntr field in struct rmid_read to indicate whether counter assignment mode is in use. Update the logic to call resctrl_arch_cntr_read() and resctrl_arch_reset_cntr() when the assignment mode is active. Report 'Unassigned' in case the user attempts to read an event without assigning a hardware counter. Suggested-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Introduce interface to display number of free MBM countersBabu Moger
Introduce the "available_mbm_cntrs" resctrl file to display the number of counters available for assignment in each domain when "mbm_event" mode is enabled. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Add resctrl file to display number of assignable countersBabu Moger
The "mbm_event" counter assignment mode allows users to assign a hardware counter to an RMID, event pair and monitor bandwidth usage as long as it is assigned. The hardware continues to track the assigned counter until it is explicitly unassigned by the user. Create 'num_mbm_cntrs' resctrl file that displays the number of counters supported in each domain. 'num_mbm_cntrs' is only visible to user space when the system supports "mbm_event" mode. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15fs/resctrl: Introduce the interface to display monitoring modesBabu Moger
Introduce the resctrl file "mbm_assign_mode" to list the supported counter assignment modes. The "mbm_event" counter assignment mode allows users to assign a hardware counter to an RMID, event pair and monitor bandwidth usage as long as it is assigned. The hardware continues to track the assigned counter until it is explicitly unassigned by the user. Each event within a resctrl group can be assigned independently in this mode. On AMD systems "mbm_event" mode is backed by the ABMC (Assignable Bandwidth Monitoring Counters) hardware feature and is enabled by default. The "default" mode is the existing mode that works without the explicit counter assignment, instead relying on dynamic counter assignment by hardware that may result in hardware not dedicating a counter resulting in monitoring data reads returning "Unavailable". Provide an interface to display the monitor modes on the system. $ cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_event] default Add IS_ENABLED(CONFIG_RESCTRL_ASSIGN_FIXED) check to support Arm64. On x86, CONFIG_RESCTRL_ASSIGN_FIXED is not defined. On Arm64, it will be defined when the "mbm_event" mode is supported. Add IS_ENABLED(CONFIG_RESCTRL_ASSIGN_FIXED) check early to ensure the user interface remains compatible with upcoming Arm64 support. IS_ENABLED() safely evaluates to 0 when the configuration is not defined. As a result, for MPAM, the display would be either: [default] or [mbm_event] Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15x86/resctrl: Add ABMC feature in the command line optionsBabu Moger
Add a kernel command-line parameter to enable or disable the exposure of the ABMC (Assignable Bandwidth Monitoring Counters) hardware feature to resctrl. Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Link: https://lore.kernel.org/cover.1757108044.git.babu.moger@amd.com
2025-09-15Merge back earlier cpufreq material for 6.18Rafael J. Wysocki
2025-09-15dt-bindings: pwm: samsung: add exynos8890 compatibleIvaylo Ivanov
Add samsung,exynos8890-pwm compatible string to binding document. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20250914132033.2622886-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
2025-09-15dt-bindings: pwm: apple,s5l-fpwm: Add t6020-fpwm compatibleJanne Grunau
The PWM controller on Apple's M2 Pro/Max SoCs behaves in the same way as on previous M1 and M2 SoCs. Add its per SoC compatible. At the same time fix the order of existing entries. The sort order logic is having SoC numeric code families in release order, and SoCs within each family in release order: - t8xxx (Apple HxxP/G series, "phone"/"tablet" chips) - t8103 (Apple H13G/M1) - t8112 (Apple H14G/M2) - t6xxx (Apple HxxJ series, "desktop" chips) - t6000/t6001/t6002 (Apple H13J(S/C/D) / M1 Pro/Max/Ultra) - t6020/t6021/t6022 (Apple H14J(S/C/D) / M2 Pro/Max/Ultra) Note that SoCs of the t600[0-2] / t602[0-2] family share the t6000 / t6020 compatible where the hardware is 100% compatible, which is usually the case in this highly related set of SoCs. Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250828-dt-apple-t6020-v1-20-507ba4c4b98e@jannau.net Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
2025-09-15dt-bindings: pwm: nxp,lpc1850-sct-pwm: Minor whitespace cleanup in exampleKrzysztof Kozlowski
The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250821083110.46420-2-krzysztof.kozlowski@linaro.org Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
2025-09-15dt-bindings: pwm: fsl,vf610-ftm-pwm: Add compatible for s32g2 and s32g3Daniel Lezcano
The S32G2 and S32G3 have a FlexTimer (FTM) available which is the same as the one found on the Vybrid Family and the i.MX8. Add the compatibles in the bindings Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250812200036.3432917-2-daniel.lezcano@linaro.org Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
2025-09-15dt-bindings: timer: renesas,rz-mtu3: Use #pwm-cells = <3>Uwe Kleine-König
With the goal to unify all PWM bindings to use #pwm-cells = <3> update the renesas,rz-mtu3 binding accordingly. Keep <2> documented as a deprecated value at least until the in-tree device trees are fixed accordingly. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250527205823.377785-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
2025-09-15powerpc/pseries: Define papr-hvpipe ioctlHaren Myneni
PowerPC FW introduced HVPIPE RTAS calls such as ibm,send-hvpipe-msg and ibm,receive-hvpipe-msg for the user space to exchange information with different sources such as Hardware Management Consoles (HMC). HVPIPE_IOC_CREATE_HANDLE is defined to use /dev/papr-hvpipe interface for ibm,send-hvpipe-msg and ibm,receive-hvpipe-msg RTAS calls. Also defined papr_hvpipe_hdr which will added in the payload that is passed between the kernel and the user space. Signed-off-by: Haren Myneni <haren@linux.ibm.com> Tested-by: Shashank MS <shashank.gowda@in.ibm.com> Reviewed-by: Mahesh Salgaonkar <mahesh@linux.ibm.com> Reviewed-by: Tyrel Datwyler <tyreld@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20250909084402.1488456-2-haren@linux.ibm.com
2025-09-15Merge tag 'v6.17-rc6' into drm-nextDave Airlie
This is a backmerge of Linux 6.17-rc6, needed for msm, also requested by misc. Signed-off-by: Dave Airlie <airlied@redhat.com>
2025-09-15Merge 6.17-rc6 into tty-nextGreg Kroah-Hartman
We need the tty/serial fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-09-15Merge 6.17-rc6 into usb-nextGreg Kroah-Hartman
We need the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-09-14Merge tag 'phy-fix-6.17' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull generic phy driver fixes from Vinod Koul: - Qualcomm repeater override properties, qmp pcie bindings fix for clocks and initialization sequence for firmware power down case - Marvell comphy bindings clock and child node constraints - Tegra xusb device reference leaks fix - TI omap usb device ref leak on unbind and RGMII IS settings fix * tag 'phy-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: qcom: qmp-pcie: Fix PHY initialization when powered down by firmware phy: ti: gmii-sel: Always write the RGMII ID setting dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings phy: ti-pipe3: fix device leak at unbind phy: ti: omap-usb2: fix device leak at unbind phy: tegra: xusb: fix device and OF node leak at probe dt-bindings: phy: marvell,comphy-cp110: Fix clock and child node constraints phy: qualcomm: phy-qcom-eusb2-repeater: fix override properties
2025-09-14Merge tag 'dmaengine-fix-6.17' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine fixes from Vinod Koul: - Intel idxd fixes for idxd_free() handling, refcount underflow on module unload, double free in idxd_setup_wqs() - Qualcomm bam dma missing properties and handing for channels with ees - dw device reference leak in rzn1_dmamux_route_allocate() * tag 'dmaengine-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: dmaengine: dw: dmamux: Fix device reference leak in rzn1_dmamux_route_allocate dmaengine: ti: edma: Fix memory allocation size for queue_priority_map dmaengine: idxd: Fix double free in idxd_setup_wqs() dmaengine: idxd: Fix refcount underflow on module unload dmaengine: idxd: Remove improper idxd_free dmaengine: qcom: bam_dma: Fix DT error handling for num-channels/ees dt-bindings: dma: qcom: bam-dma: Add missing required properties
2025-09-14dt-bindings: net: ti: Adds DUAL-EMAC mode support on PRU-ICSS2 for AM57xx, ↵Parvathi Pudi
AM43xx and AM33xx SOCs Documentation update for the newly added "pruss2_eth" device tree node and its dependencies along with compatibility for PRU-ICSS Industrial Ethernet Peripheral (IEP), PRU-ICSS Enhanced Capture (eCAP) peripheral and using YAML binding document for AM57xx SoCs. Reviewed-by: Mohan Reddy Putluru <pmohan@couthit.com> Co-developed-by: Basharath Hussain Khaja <basharath@couthit.com> Signed-off-by: Basharath Hussain Khaja <basharath@couthit.com> Signed-off-by: Parvathi Pudi <parvathi@couthit.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250912104741.528721-2-parvathi@couthit.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-14spi: dt-bindings: apple,spi: Add t6020-spi compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,spi" anymore [1]. Use "apple,t8103-spi" as base compatible as it is the SoC the driver and bindings were written for. The SPI controller on Apple M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-spi" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14ASoC: dt-bindings: apple,mca: Add t6020-mca compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,mca" anymore [1]. Use "apple,t8103-mca" as base compatible as it is the SoC the driver and bindings were written for. mca on Apple's M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-mca" so add its per-SoC compatible with the former as fallbeck used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: dma: apple,admac: Add t6020-admac compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,admac" anymore [1]. Use "apple,t8103-admac" as base compatible as it is the SoC the driver and bindings were written for. admac on Apple's M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-admac" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: clock: apple,nco: Add t6020-nco compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,nco" anymore [1]. Use "apple,t8103-nco" as base compatible as it is the SoC the driver and bindings were written for. The block found on Apple's M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-nco" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: watchdog: apple,wdt: Add t6020-wdt compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,wdt" anymore [1]. Use "apple,t8103-wdt" as base compatible as it is the SoC the driver and bindings were written for. The block on the Apple M2 Pro/Max/Ultra SoCs is compatible with the existing driver so add its per-SoC compatible. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: spmi: apple,spmi: Add t6020-spmi compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,spmi" anymore [1]. Use "apple,t8103-spmi" as base compatible as it is the SoC the driver and bindings were written for. The SPMI controller on Apple M2 Pro/Max/Ultra is compatible to "apple,t8103-spmi" so add its per-SoC compatible with the former as fallback used by the existing driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: mfd: apple,smc: Add t6020-smc compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,smc" anymore [1]. Use "apple,t8103-smc" as base compatible as it is the SoC the driver and bindings were written for. SMC on Apple's M2 Pro/Max/Ultra SoCs is compatible with the existing driver so add its per-SoC compatible with the new base compatible as fallback used by the driver. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: net: bcm4329-fmac: Add BCM4388 PCI compatibleJanne Grunau
BCM4388 WiFi/BT modules are found on Apple silicon devices using M2 Pro/Max/Ultra and later. Driver support for this module is not submitted yet. Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: net: bcm4377-bluetooth: Add BCM4388 compatibleJanne Grunau
Add BCM4388 PCI vendor/product ID as compatible. The BCM4388 WiFi/BT module is found on Apple silicon devices with M2 Pro/Max/Ultra and later. Support for this variant was added in 2024 without amending the dt-bindings. Link: https://lore.kernel.org/asahi/20240602-btbcm4388-v1-1-210e4b4eeb3b@svenpeter.dev/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: nvme: apple: Add apple,t6020-nvme-ans2 compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,nvme-ans2" anymore [1]. Add "apple,t8103-nvme-ans2" as fallback compatible as it is the SoC the driver and bindings were written for. Invert the condition for the 2 or 3 power-domains check to allow using "apple,t8103-nvme-ans2" as base compatible. "apple,t6020-nvme-ans2" on Apple M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-nvme-ans2" so add its per-SoC compatible. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: iommu: apple,sart: Add apple,t6020-sart compatibleJanne Grunau
"apple,t6020-sart" as found in Apple's M2 Pro/Max/Ultra SoCs is compatible with SART3 used in t6000. Add its per-SoC compatible to allow a distinction should it become necessary. Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: gpu: apple,agx: Add agx-{g14s,g14c,g14d} compatiblesJanne Grunau
Add compatibles for the GPU variants found on Apple's M2 Pro/Max/Ultra SoCs. Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: mailbox: apple,mailbox: Add t6020 compatibleJanne Grunau
The mailbox hardware remains unchanged on M2 Pro/Max/Ultra SoCs so just add its per-SoC compatible. Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: pinctrl: apple,pinctrl: Add apple,t6020-pinctrl compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,pinctrl" anymore [1]. Use "apple,t8103-pinctrl" as fallback compatible as it is the SoC the driver and bindings were written for. The M2 Pro/Max/Ultra SoCs use the same pinctrl hardware, so just add its per-SoC compatible using the new base as fallback. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: iommu: dart: Add apple,t6020-dart compatibleJanne Grunau
t6020-dart is compatible to t8110-dart and annotated as such in Apple's device tree. Add its per-SoC compatible in case t6020 specific handling becomes necessary. The dart instances on M2 Pro/Max/Ultra based SoCs differ in one aspect from the M2 based ones. They indicate an IAS of 42 requiring implementing support for a fouth page table level in the dart driver and its io-pgtable [1]. [1]: https://lore.kernel.org/asahi/20250821-apple-dart-4levels-v2-0-e39af79daa37@jannau.net/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: interrupt-controller: apple,aic2: Add apple,t6020-aic compatibleJanne Grunau
The Apple M2 Pro/Max/Ultra SoCs use AIC2 as interrupt controller. This is the final SoC added as compatible as Apple M3 and later use AIC3. Apple's A15 uses AIC2 as well but has no official support for alternate operating systems. Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: cpufreq: apple,cluster-cpufreq: Add t6020 compatibleJanne Grunau
The CPU frequency control on M2 Pro/Max/Ultra SoCs is compatible to the M2 (T8112) one. So add this with the per-SoC compatible to the bindings. Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: power: apple,pmgr-pwrstate: Add t6020 compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,pmgr-pwrstate" anymore [1]. Use "apple,t8103-pmgr-pwrstate" as base compatible as it is the SoC the driver and bindings were written for. The implementation on Apple M2 Pro/Max/Ultra SoCs is compatible so add its per-SoC compatible with the new base. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: arm: apple: apple,pmgr: Add t6020-pmgr compatibleJanne Grunau
After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,pmgr" anymore [1]. Use "apple,t8103-pmgr" as base compatible as it is the SoC the bindings were written for. The block on Apple M2 Pro/Max/Ultra SoCs is compatible with "apple,t8103-pmgr" so use it as fallback compatible and add t6020 as per-SoC compatible. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net>
2025-09-14dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/T2H and RZ/N2H SoCsLad Prabhakar
Add device tree binding support for the Gigabit Ethernet MAC (GMAC) IP on Renesas RZ/T2H and RZ/N2H SoCs. While these SoCs use the same Synopsys DesignWare MAC version 5.20 as RZ/V2H, they are synthesized with different hardware configurations. Add new compatible strings "renesas,r9a09g077-gbeth" for RZ/T2H and "renesas,r9a09g087-gbeth" for RZ/N2H, with the latter using RZ/T2H as fallback since they share identical GMAC IP. Update the schema to handle hardware differences between SoC variants. RZ/T2H requires only 3 clocks compared to 7 on RZ/V2H, supports 8 RX/TX queue pairs instead of 4, and needs 2 reset controls with reset-names property versus a single unnamed reset. RZ/T2H also has the split header feature enabled which is disabled on RZ/V2H. Add support for an optional pcs-handle property to connect the GMAC to the MIIC PCS converter on RZ/T2H. Use conditional schema validation to enforce the correct clock, reset, and interrupt configurations per SoC variant. Extend the base snps,dwmac.yaml schema to accommodate the increased interrupt count, supporting up to 19 interrupts and extending the rx-queue and tx-queue interrupt name patterns to cover queues 0-7. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250908105901.3198975-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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