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2025-10-13pinctrl: Demote subsystem banner messageLinus Walleij
There is no reason to print any "hello world" from pin control unless (maybe) if we are debugging. Drop the banner. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13riscv: dts: spacemit: add UART pinctrl combinationsHendrik Hamerlinck
Add UART pinctrl configurations based on the SoC datasheet and the downstream Bianbu Linux tree. The drive strength values were taken from the downstream implementation, which uses medium drive strength. CTS/RTS are moved to separate *-cts-rts-cfg states so boards can enable hardware flow control conditionally. Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20250917065907.160615-1-hendrik.hamerlinck@hammernet.be Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-10-13spi: cadence-quadspi: Fix pm_runtime unbalance on dma EPROBE_DEFERMattijs Korpershoek
In csqspi_probe(), when cqspi_request_mmap_dma() returns -EPROBE_DEFER, we handle the error by jumping to probe_setup_failed. In that label, we call pm_runtime_disable(), even if we never called pm_runtime_enable() before. Because of this, the driver cannot probe: [ 2.690018] cadence-qspi 47040000.spi: No Rx DMA available [ 2.699735] spi-nor spi0.0: resume failed with -13 [ 2.699741] spi-nor: probe of spi0.0 failed with error -13 Only call pm_runtime_disable() if it was enabled by adding a new label to handle cqspi_request_mmap_dma() failures. Fixes: b07f349d1864 ("spi: spi-cadence-quadspi: Fix pm runtime unbalance") Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://patch.msgid.link/20251009-cadence-quadspi-fix-pm-runtime-v2-1-8bdfefc43902@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: spi-nxp-fspi: limit the clock rate for different sample clock source ↵Haibo Chen
selection For different sample clock source selection, the max frequency flexspi supported are different. For mode 0, max frequency is 66MHz. For mode 3, the max frequency is 166MHz. Refer to 3.9.9 FlexSPI timing parameters on page 65. https://www.nxp.com/docs/en/data-sheet/IMX8MNCEC.pdf Though flexspi maybe still work under higher frequency, but can't guarantee the stability. IC suggest to add this limitation on all SoCs which contain flexspi. Fixes: c07f27032317 ("spi: spi-nxp-fspi: add the support for sample data from DQS pad") Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20250922-fspi-fix-v1-3-ff4315359d31@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: spi-nxp-fspi: add extra delay after dll lockedHan Xu
Due to the erratum ERR050272, the DLL lock status register STS2 [xREFLOCK, xSLVLOCK] bit may indicate DLL is locked before DLL is actually locked. Add an extra 4us delay as a workaround. refer to ERR050272, on Page 20. https://www.nxp.com/docs/en/errata/IMX8_1N94W.pdf Fixes: 99d822b3adc4 ("spi: spi-nxp-fspi: use DLL calibration when clock rate > 100MHz") Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20250922-fspi-fix-v1-2-ff4315359d31@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: spi-nxp-fspi: re-config the clock rate when operation require new clock ↵Haibo Chen
rate Current operation contain the max_freq, so new coming operation may use new clock rate, need to re-config the clock rate to match the requirement. Fixes: 26851cf65ffc ("spi: nxp-fspi: Support per spi-mem operation frequency switches") Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20250922-fspi-fix-v1-1-ff4315359d31@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: Merge up v6.18-rc1Mark Brown
Ensure my CI has a sensible baseline.
2025-10-13dt-bindings: pinctrl: qcom,sm6115-lpass-lpi: add QCM2290 compatibleAlexey Klimov
Add a compatible for the LPASS LPI pin controller on QCM2290. It seems to be compatible with sm6115 LPASS pinctrl. Cc: Konrad Dybcio <konradybcio@kernel.org> Cc: Srinivas Kandagatla <srini@kernel.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13ASoC: nau8821: Avoid unnecessary blocking in IRQ handlerCristian Ciocaltea
The interrupt handler offloads the microphone detection logic to nau8821_jdet_work(), which implies a sleep operation. However, before being able to process any subsequent hotplug event, the interrupt handler needs to wait for any prior scheduled work to complete. Move the sleep out of jdet_work by converting it to a delayed work. This eliminates the undesired blocking in the interrupt handler when attempting to cancel a recently scheduled work item and should help reducing transient input reports that might confuse user-space. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20251003-nau8821-jdet-fixes-v1-5-f7b0e2543f09@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: nau8821: Add DMI quirk to bypass jack debounce circuitCristian Ciocaltea
Stress testing the audio jack hotplug handling on a few Steam Deck units revealed that the debounce circuit is responsible for having a negative impact on the detection reliability, e.g. in some cases the ejection interrupt is not fired, while in other instances it goes into a kind of invalid state and generates a flood of misleading interrupts. Add new entries to the DMI table introduced via commit 1bc40efdaf4a ("ASoC: nau8821: Add DMI quirk mechanism for active-high jack-detect") and extend the quirk logic to allow bypassing the debounce circuit used for jack detection on Valve Steam Deck LCD and OLED models. While at it, rename existing NAU8821_JD_ACTIVE_HIGH quirk bitfield to NAU8821_QUIRK_JD_ACTIVE_HIGH. This should help improve code readability by differentiating from similarly named register bits. Fixes: aab1ad11d69f ("ASoC: nau8821: new driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20251003-nau8821-jdet-fixes-v1-4-f7b0e2543f09@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: nau8821: Consistently clear interrupts before unmaskingCristian Ciocaltea
The interrupt handler attempts to perform some IRQ status clear operations *after* rather than *before* unmasking and enabling interrupts. This is a rather fragile approach since it may generally lead to missing IRQ requests or causing spurious interrupts. Make use of the nau8821_irq_status_clear() helper instead of manipulating the related register directly and ensure any interrupt clearing is performed *after* the target interrupts are disabled/masked and *before* proceeding with additional interrupt unmasking/enablement operations. This also implicitly drops the redundant clear operation of the ejection IRQ in the interrupt handler, since nau8821_eject_jack() has been already responsible for clearing all active interrupts. Fixes: aab1ad11d69f ("ASoC: nau8821: new driver") Fixes: 2551b6e89936 ("ASoC: nau8821: Add headset button detection") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20251003-nau8821-jdet-fixes-v1-3-f7b0e2543f09@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: nau8821: Generalize helper to clear IRQ statusCristian Ciocaltea
Instead of adding yet another utility function for dealing with the interrupt clearing register, generalize nau8821_int_status_clear_all() by renaming it to nau8821_irq_status_clear(), whilst introducing a second parameter to allow restricting the operation scope to a single interrupt instead of the whole range of active IRQs. While at it, also fix a spelling typo in the comment block. Note this is mainly a prerequisite for subsequent patches aiming to address some deficiencies in the implementation of the interrupt handler. Thus the presence of the Fixes tag below is intentional, to facilitate backporting. Fixes: aab1ad11d69f ("ASoC: nau8821: new driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20251003-nau8821-jdet-fixes-v1-2-f7b0e2543f09@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: nau8821: Cancel jdet_work before handling jack ejectionCristian Ciocaltea
The microphone detection work scheduled by a prior jack insertion interrupt may still be in a pending state or under execution when a jack ejection interrupt has been fired. This might lead to a racing condition or nau8821_jdet_work() completing after nau8821_eject_jack(), which will override the currently disconnected state of the jack and incorrectly report the headphone or the headset as being connected. Cancel any pending jdet_work or wait for its execution to finish before attempting to handle the ejection interrupt. Proceed similarly before launching the eject handler as a consequence of detecting an invalid insert interrupt. Fixes: aab1ad11d69f ("ASoC: nau8821: new driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patch.msgid.link/20251003-nau8821-jdet-fixes-v1-1-f7b0e2543f09@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13dt-bindings: sound: Update ADMAIF bindings for tegra264sheetal
Update the ADMAIF bindings as tegra264 supports 64 channels, which includes 32 RX and 32 TX channels. Signed-off-by: sheetal <sheetal@nvidia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250929105930.1767294-3-sheetal@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13rpmb: move rpmb_frame struct and constants to common headerBean Huo
Move struct rpmb_frame and RPMB operation constants from MMC block driver to include/linux/rpmb.h for reuse across different RPMB implementations (UFS, NVMe, etc.). Signed-off-by: Bean Huo <beanhuo@micron.com> Reviewed-by: Avri Altman <avri.altman@sandisk.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-10-13pinctrl: mediatek: mt8189: align register base names to dt-bindings onesLouis-Alexis Eyraud
The mt8189-pinctrl driver requires to probe that a device tree uses in the device node the same names than mt8189_pinctrl_register_base_names array. But they are not matching the required ones in the "mediatek,mt8189-pinctrl" dt-bindings, leading to possible dtbs check issues. The mt8189_pinctrl_register_base_names entry order is also different. So, align all mt8189_pinctrl_register_base_names entry names and order on dt-bindings. Fixes: a3fe1324c3c5 ("pinctrl: mediatek: Add pinctrl driver for mt8189") Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13pinctrl: mediatek: mt8196: align register base names to dt-bindings onesLouis-Alexis Eyraud
The mt8196-pinctrl driver requires to probe that a device tree uses in the device node the same names than mt8196_pinctrl_register_base_names array. But they are not matching the required ones in the "mediatek,mt8196-pinctrl" dt-bindings, leading to possible dtbs check issues. So, align all mt8196_pinctrl_register_base_names entries on dt-bindings ones. Fixes: f7a29377c253 ("pinctrl: mediatek: Add pinctrl driver on mt8196") Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13spi: dt-bindings: spi-qpic-snand: Add IPQ5332 compatibleMd Sadre Alam
IPQ5332 contains the QPIC-SPI-NAND flash controller which is the same as the one found in IPQ9574. So let's document the IPQ5332 compatible and use IPQ9574 as the fallback. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20251008090413.458791-3-quic_mdalam@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: dt-bindings: spi-qpic-snand: Add IPQ5424 compatibleMd Sadre Alam
IPQ5424 contains the QPIC-SPI-NAND flash controller which is the same as the one found in IPQ9574. So let's document the IPQ5424 compatible and use IPQ9574 as the fallback. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20251008090413.458791-2-quic_mdalam@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: offload: Add offset parameterAxel Haslam
Add an offset parameter that can be passed in the periodic trigger. This is useful for example when ADC drivers implement a separate periodic signal to trigger conversion and need offload to read the result with some delay. While at it, add some documentation to offload periodic trigger parameters. Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Axel Haslam <ahaslam@baylibre.com> Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Link: https://patch.msgid.link/cd315e95c0bd8523f00e91c400abcd6a418e5924.1759760519.git.marcelo.schmitt@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: aspeed: Only map necessary address window regionChin-Ting Kuo
Previously, the driver mapped the entire SPI address decoding region during probe. On systems with small flash or limited memory, this could lead to excessive memory usage or allocation failures. This patch changes the strategy to initially map a small address window for SPI flash device probing. After determining each chip select's flash size, the driver unmaps the temporary region and remaps only the required address window accordingly. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Link: https://patch.msgid.link/20251001112605.1130723-7-chin-ting_kuo@aspeedtech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: aspeed: Add per-platform adjust_window callback for decoding rangeChin-Ting Kuo
Different ASPEED SoCs have specific limitations on SPI address decoding, such as total range size, minimum window size per CS, and alignment requirements. The original adjustment logic only handles simple cases and could fail in more complex setups found in advanced board designs, e.g., small flash on CS0 and large flash on CS1, or when the total physical flash size exceeds the decoding range supported by the SPI controller. This patch introduces a per-platform adjust_window callback to handle these constraints properly. Each platform defines its own logic to adjust decoding ranges, trim excess size, and ensure alignment. If trimming is required, the affected CS will fall back to user mode access to ensure the entire flash remains accessible from the MTD layer. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Link: https://patch.msgid.link/20251001112605.1130723-6-chin-ting_kuo@aspeedtech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: aspeed: Centralize address decoding region managementChin-Ting Kuo
The original approach to handling address decoding overlaps was to trim the next region directly. If the next CS's decoding range was fully overlapped by the current one, it would be forcibly closed by trimming its size to zero. This could lead expected behavior, especially on the platform with multiple flashes layout. To solve improper trimming problem, this patch collects the required address decoding size at each stage, then, (re-)arragne address decoding region to each CS centrally with knowing the total AHB decoding size. If a segment register cannot be updated (e.g. due to bootloader write protection), the original value is kept to avoid breaking access and an error is reported if the total decoding size of all CS exceeds the total AHB decoding size. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Link: https://patch.msgid.link/20251001112605.1130723-5-chin-ting_kuo@aspeedtech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: aspeed: Force default address decoding range assignment for each CSChin-Ting Kuo
On some platforms, we cannot assume that the whole address decoding range value is ready for each CS. Especially for chip selects other than CS0, the address decoding range may not be properly configured before the kernel stage, or the existing configuration may be unsuitable. This can lead to SPI flash detection failures during driver probe. To ensure reliable initialization, this patch forcibly assigns a default address decoding range to each chip select based on a platform-specific minimum window size. Unused chip selects are explicitly disabled to avoid conflicts. This change improves robustness across platforms with varying bootloader behavior and ensures consistent SPI flash initialization. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Link: https://patch.msgid.link/20251001112605.1130723-4-chin-ting_kuo@aspeedtech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: aspeed: Improve timing calibration algorithm for AST2600 platformChin-Ting Kuo
Starting with the AST2600 platform, most platfom manufacturers have adopted more complex board designs and signal routing, making SPI timing calibration increasingly sensitive and critical. Previously, the driver selected the first "PASS" timing point during calibration, which may not yield the most stable result. This patch introduces a more robust calibration method: - It evaluates all combinations of HCLK sample point delay and DI input delay. The results are stored in a 2D buffer for further comparison. - Because the timing delay behavior is non-linear across HCLK sample points, the optimal timing point is selected as the center of the longest consecutive "PASS" interval within a single HCLK sample point row. This approach ensures better stability and precision in SPI read timing, especially under complex signal integrity conditions. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Link: https://patch.msgid.link/20251001112605.1130723-3-chin-ting_kuo@aspeedtech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: aspeed: Update clock selection strategyChin-Ting Kuo
This patch updates the SPI clock selection logic for cases where timing calibration is not performed or the results are failed. Timing calibration process is skipped in the two scenarios below. - Low-entropy data in the calibration region: The driver skips timing calibration if the data read from the SPI flash contains mostly 0x00 or 0xFF. Originally, the driver used a low-frequency clock to read this region as golden data. However, due to variations in host characteristics and image layout, we cannot assume sufficient entropy in this region to ensure reliable calibration. - Low-speed configurations (< 40MHz): The ASPEED SPI controller does not support timing calibration when the max_speed_hz of the SPI device is below 40MHz. In both cases, the SPI clock frequency specified in the device tree should be used directly. When timing calibration is skipped, it is the board vendor's responsibility to ensure that the SPI flash SI (Signal Integrity) is sufficient for reliable operation at the configured frequency. When timing calibration processes is execued and all potential clock frequencies are performed, but are all failed, the lower clock frequency should be adopted to ensure the overall system can boot up successfully. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Link: https://patch.msgid.link/20251001112605.1130723-2-chin-ting_kuo@aspeedtech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: dw: add target mode supportBenoît Monin
Implement target mode for the DesignWare controller with the following changes: Allocate an SPI controller of the correct type based on the spi-slave property in dw_spi_add_controller() and set the controller properties depending on its type. Since they are only relevant when acting as a host controller, settings related to chip-select control and the set_cs() callback are only set in host mode, as are the loopback support, the memory operations and the maximum frequency. The target_abort() callback is set only when configured in target mode. The number of chip-select is set to 1 in dw_spi_hw_init() since the controller only has one CS input in target mode. In dw_spi_update_config(), return after setting the CTRLR0 register as the other registers are only relevant in host mode and are read-only in target mode. This function is called as part of the transfer_one() callback, which is identical in both the host and target mode. Move the code implementing the handle_err() callback to a new function named dw_spi_abort(), and use it to implement both the handle_err() and the target_abort() callbacks. Finally, drop the error path on the spi-slave property in dw_spi_mmio_probe(), as it is now a valid configuration. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Link: https://patch.msgid.link/20251002-spi-dw-target-v1-2-993e91c1a712@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13spi: dw: rename the spi controller to ctlrBenoît Monin
Since the designware SPI controller can act as both a target and a host, rename spi_controller member of the dw_spi struct to ctlr instead of host. Similarly, rename the functions handling the controller, using controller instead of host as the suffix. No functional changes intended. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Link: https://patch.msgid.link/20251002-spi-dw-target-v1-1-993e91c1a712@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13regulator: dt-bindings: Convert Dialog DA9211 Regulators to DT schemaAriel D'Alessandro
Convert the existing text-based DT bindings for Dialog Semiconductor DA9211 Voltage Regulators family to a DT schema. Examples are simplified, as these are all equal. Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20251001183648.83379-1-ariel.dalessandro@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: codecs: Fix the error of excessive semicolonsTang Bin
Remove unnecessary semicolons in the function pm4125_codec_enable_adc and pm4125_micbias_control. Signed-off-by: Tang Bin <tangbin@cmss.chinamobile.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20250930094103.2038-1-tangbin@cmss.chinamobile.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoc: tas2783A: Remove unneeded variable assignmentTang Bin
In the function tas2783_update_calibdata, 'i' to 0 is repeated, thus delete one. Signed-off-by: Tang Bin <tangbin@cmss.chinamobile.com> Link: https://patch.msgid.link/20250930093349.1934-1-tangbin@cmss.chinamobile.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: dt-bindings: ti,tas2781: Add TAS5802, TAS5815, and TAS5828Baojun Xu
TAS5802, TAS5815, and TAS5828 are in same family with TAS5825, TAS5827, TAS5802 and TAS5815 share same address setting, and TAS5828 share same address setting with TAS5827. Signed-off-by: Baojun Xu <baojun.xu@ti.com> Link: https://patch.msgid.link/20251010085349.52951-2-baojun.xu@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: tas2781: Add TAS5802, TAS5815, and TAS5828Baojun Xu
TAS5802/TAS5815/TAS5828 has on-chip DSP without current/voltage feedback. Signed-off-by: Baojun Xu <baojun.xu@ti.com> Link: https://patch.msgid.link/20251010085349.52951-1-baojun.xu@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13pinctrl: qcom: add the tlmm driver for Kaanapali platformsJingyi Wang
Add support for Kaanapali TLMM configuration and control via the pinctrl framework. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13dt-bindings: pinctrl: describe Kaanapali TLMMJingyi Wang
The Top Level Mode Multiplexer (TLMM) in the Kaanapali SoC provide GPIO and pinctrl functionality for UFS, SDC and 217 GPIO pins. Add a DeviceTree binding to describe the Kaanapali TLMM block. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13dt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schemaRob Herring (Arm)
Convert the marvell,armada3710-(sb|nb)-pinctrl binding to DT schema format. The binding includes the "marvell,armada-3700-xtal-clock" subnode which is simple enough to include here. Mark interrupt-controller/#interrupt-cells as required as the users have them and the h/w is either capable of interrupts or not. As this syscon has 2 register ranges, syscon-common.yaml needs to be updated to drop the restriction of 1 register entry. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13ASoC: sof-function-topology-lib: escalate the log when missing function ↵Bard Liao
topoplogy Function topology must be used if the ACPI match table is created based on the reported ACPI table because the monolithic topology is not picked for the audio configuration. Escalate the log and ask the user to download the latest topologies. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Simon Trimmer <simont@opensource.cirrus.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://patch.msgid.link/20251009094023.3474895-10-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: SOF: Intel: use sof_sdw as default SDW machine driverBard Liao
If there is no SoundWire machine matches the existing acpi match table, get the required machine data from the acpi table and construct the link adrs and endpoints. Pass the data to the default Intel SoundWire machine driver. And we don't need to add new item to the acpi match table in common cases. We will construct a dummy topology name. The dummy topology is just used to extract the platform name for function topology and should not be used. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Simon Trimmer <simont@opensource.cirrus.com> Link: https://patch.msgid.link/20251009094023.3474895-9-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: SOF: don't check the existence of dummy topologyBard Liao
Monolithic topology is not needed if function topology is used. Instead of creating a dummy topology in the file system, we can skip the existence check in the kernel. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Simon Trimmer <simont@opensource.cirrus.com> Link: https://patch.msgid.link/20251009094023.3474895-8-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: SOF: add platform name into sof_intel_dsp_descBard Liao
The platform name will be used construct the topology name. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Simon Trimmer <simont@opensource.cirrus.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://patch.msgid.link/20251009094023.3474895-7-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: soc_sdw_utils: export asoc_sdw_get_dai_typeBard Liao
asoc_sdw_get_dai_type() is quite useful to convert SDCA function types to SDW DAI types. It can be used by other drivers. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Simon Trimmer <simont@opensource.cirrus.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://patch.msgid.link/20251009094023.3474895-6-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: Intel: export sof_sdw_get_tplg_filesBard Liao
The sof_sdw_get_tplg_files function is a callback of snd_soc_acpi_mach. Export it to allow other modules to use it. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Simon Trimmer <simont@opensource.cirrus.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://patch.msgid.link/20251009094023.3474895-5-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: soc_sdw_utils: add name_prefix to asoc_sdw_codec_info structBard Liao
Currently, the codec name_prefix of Intel SoundWire machine driver is from the ACPI match table. We can have it in the asoc_sdw_codec_info struct as a default name_prefix of a codec if there is no corresponding audio config found in the ACPI match table. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Simon Trimmer <simont@opensource.cirrus.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://patch.msgid.link/20251009094023.3474895-4-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: soc-acpi: make some variables of acpi adr and link adr non-constBard Liao
Currently, we use predefined snd_soc_acpi_link_adr tables to match the link adr from ACPI table to select the machine driver and the topology. However, with the mechanism, we need to create the snd_soc_acpi_link_adr table for each audio config. The sof_sdw machine driver is used by almost all Intel platforms with SOF and we can load required topology file dynamically today. In other words, we can use sof_sdw machine driver as the default machine driver for Intel SOF SoundWire codecs and no need to create snd_soc_acpi_link_adr table for every new audio configs. To achieve it, we need to drop the const for some members and edit the link adr and acpi adr data to match the data from the ACPI table. Suggested-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Simon Trimmer <simont@opensource.cirrus.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://patch.msgid.link/20251009094023.3474895-3-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13ASoC: SOF: Don't print the monolithic topology name if function topology may ↵Bard Liao
be used It may confuse people if "Topology file:" is printed but the topology file is not really used. We keep the print if the topology file is missing thus user can know what topology is missed in the file system. And increase the log level to info for the actual topology that is used. So that user can get which topology is used. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Simon Trimmer <simont@opensource.cirrus.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://patch.msgid.link/20251009094023.3474895-2-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-13dt-bindings: pinctrl: Convert Marvell Berlin pinctrl to DT schemaRob Herring (Arm)
Convert the Marvell/Synaptics Berlin pinctrl binding to DT schema format. The "reg" property was not documented for the newer SoCs. Otherwise, it's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13pinctrl: qcom: spmi-gpio: add support for {LV_VIN2, MV_VIN3}_CLK subtypesSubbaraman Narayanamurthy
Add support for SPMI PMIC GPIO subtypes GPIO_LV_VIN2_CLK and GPIO_MV_VIN3_CLK. Signed-off-by: Subbaraman Narayanamurthy <subbaraman.narayanamurthy@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13pinctrl: qcom: spmi-gpio: Add PMCX0102, PMK8850 & PMH01XX PMICs supportAnjelique Melendez
Add support for PMCX0102, PMH0101, PMH0104, PMH0110 and PMK8850 PMIC GPIOs with adding appropriate compatible strings. Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13dt-bindings: pinctrl: qcom,pmic-gpio: Add GPIO bindings for Glymur PMICsJishnu Prakash
Update the Qualcomm Technologies, Inc. PMIC GPIO binding documentation to include compatible strings for PMK8850, PMH0101, PMH0104, PMH0110 and PMCX0102 PMICs. Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-10-13pinctrl: qcom: glymur: Fix the gpio and egpio pin functionsAbel Vesa
Mark the gpio/egpio as GPIO specific pin functions, othewise the pin muxing generic framework will complain about the gpio being already requested by a different owner. Fixes: 87ebcd8baebf ("pinctrl: qcom: Add glymur pinctrl driver") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.3 (git 2.53.0) at 2026-11-12 04:48:13 +0000