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2025-10-27iommu/pages: use folio_nr_pages() instead of shift operationPedro Demarchi Gomes
folio_nr_pages() is a faster helper function to get the number of pages when NR_PAGES_IN_LARGE_FOLIO is enabled. Signed-off-by: Pedro Demarchi Gomes <pedrodemargomes@gmail.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2025-10-27RDMA/cm: Base cm_id destruction timeout on CMA valuesHåkon Bugge
When a GSI MAD packet is sent on the QP, it will potentially be retried CMA_MAX_CM_RETRIES times with a timeout value of: 4.096usec * 2 ^ CMA_CM_RESPONSE_TIMEOUT The above equates to ~64 seconds using the default CMA values. The cm_id_priv's refcount will be incremented for this period. Therefore, the timeout value waiting for a cm_id destruction must be based on the effective timeout of MAD packets. To provide additional leeway, we add 25% to this timeout and use that instead of the constant 10 seconds timeout, which may result in false negatives. Signed-off-by: Håkon Bugge <haakon.bugge@oracle.com> Link: https://patch.msgid.link/20251021132738.4179604-1-haakon.bugge@oracle.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
2025-10-27clk: renesas: r9a09g056: Add clock and reset entries for ISPLad Prabhakar
Add entries detailing the clocks and resets for the ISP in the RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023210724.666476-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-27clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resetsLad Prabhakar
Add support for the PLLVDO clock and its related CRU clocks and reset entries in the R9A09G056 CPG driver. Introduce `CLK_PLLVDO` and associated clocks like `CLK_PLLVDO_CRU0` and `CLK_PLLVDO_CRU1`, along with their corresponding dividers. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023210724.666476-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-27clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modulesLad Prabhakar
Add clock and reset definitions required to support the DSI and LCDC hardware blocks on the RZ/V2N SoC. This includes new core clocks, clock dividers, module clocks, and reset entries, as well as PLL and divider configurations specific to these peripherals. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023210724.666476-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-27clk: renesas: r9a09g077: Add TSU module clockCosmin Tanislav
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a TSU peripheral which is controlled by a module clock. The TSU module clock is enabled in register MSTPCRD (0x30c), at bit 7, resulting in a (0x30c - 0x300) / 4 * 100 + 7 = 307 index. Add it to the list of module clocks. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023081925.2412325-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-27clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDCLad Prabhakar
Add clock and reset entries for the DSI and LCDC peripherals. Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251015192611.241920-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-27Merge tag 'clk-renesas-rzv2h-plldsi-tag' into renesas-clk-for-v6.19Geert Uytterhoeven
clk: renesas: rzv2h: Add support for DSI clocks RZ/V2H Clock Pulse Generator PLLDSI API, shared by clock and MIPI DSI driver source files.
2025-10-27irqchip/sifive-plic: Add support for UltraRISC DP1000 PLICCharles Mirabile
Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to work around a known hardware bug with IRQ claiming in the UR-CP100 cores. When claiming an interrupt on UR-CP100 cores, all other interrupts must be disabled before the claim register is accessed to prevent incorrect handling of the interrupt. This is a hardware bug in the CP100 core implementation, not specific to the DP1000 SoC. When the PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM flag is present, a specialized handler (plic_handle_irq_cp100) disables all interrupts except for the first pending one before reading the claim register, and then restores the interrupts before further processing of the claimed interrupt continues. This implementation leverages the enable_save optimization, which maintains the current interrupt enable state in memory, avoiding additional register reads during the workaround. The driver matches on "ultrarisc,cp100-plic" to apply the quirk to all SoCs using UR-CP100 cores, regardless of the specific SoC implementation. This has no impact on other platforms. [ tglx: Condensed the code a bit, massaged change log and comments ] Co-developed-by: Zhang Xincheng <zhangxincheng@ultrarisc.com> Signed-off-by: Zhang Xincheng <zhangxincheng@ultrarisc.com> Signed-off-by: Charles Mirabile <cmirabil@redhat.com> Signed-off-by: Lucas Zampieri <lzampier@redhat.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Samuel Holland <samuel.holland@sifive.com> Link: https://patch.msgid.link/20251024083647.475239-5-lzampier@redhat.com
2025-10-27spi: spi-mem: Trace exec_opSean Anderson
The spi subsystem has tracing, which is very convenient when debugging problems. Add tracing for spi-mem too so that accesses that skip the spi subsystem can still be seen. The format is roughly based on the existing spi tracing. We don't bother tracing the op's address because the tracing happens while the memory is locked, so there can be no confusion about the matching of start and stop. The conversion of cmd/addr/dummy to an array is directly analogous to the conversion in the latter half of spi_mem_exec_op. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://patch.msgid.link/20251021144702.1582397-1-sean.anderson@linux.dev Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Add SPI bus support for cs530x partsVitaly Rodionov
Cirrus Logic cs530x device family has 2 control buses I2C and SPI. This patch adds SPI support. Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-13-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: dt-bindings: sound: cirrus: cs530x: Add SPI bus supportVitaly Rodionov
The CS530x device family supports multiple control interfaces. At present, only the I2C interface is implemented. Adding support for the SPI control interface, operating at up to 24 MHz. Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-12-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Rename i2c related structuresSimon Trimmer
In preparation for SPI support these structures should be renamed to reflect that they are for i2c. Signed-off-by: Simon Trimmer <simont@opensource.cirrus.com> Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-11-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Correct MCLK reference frequency valuesVitaly Rodionov
The MCLK frequency must be 49.152 MHz (for 48 kHz-related sample rates) or 45.1584 MHz (for 44.1 kHz-related sample rates). Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-10-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Check the DEVID matches the devtypeSimon Trimmer
If the read device ID is not the expected devtype derived from the compatible device match then fail the probe as other configuration details may be incorrect. Signed-off-by: Simon Trimmer <simont@opensource.cirrus.com> Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-9-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Rename bitfield to reflect common use for ADC and DACVitaly Rodionov
Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-8-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Add CODEC and DAC supportSimon Trimmer
- Added DAC register address constants - Add the new registers to the regmap config - Renamed constants that are shared between the DACs and ADCs - Add the device IDs and device names of the CODEC and DACs along with their different capabilities - Add DAPM widgets, ALSA controls and event handling for the DAC functionality - Add Playback DAI support Signed-off-by: Simon Trimmer <simont@opensource.cirrus.com> Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-7-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: dt-bindings: sound: cirrus: cs530x: Add cs530xVitaly Rodionov
This patch adds additional cs530x family variants. cirrus,cs4282 - high-performance, 32-bit resolution, stereo CODEC cirrus,cs4302 - high performance stereo DAC, 2 channels cirrus,cs4304 - high performance stereo DAC, 4 channels cirrus,cs4308 - high performance stereo DAC, 8 channels Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251023090327.58275-6-vitalyr@opensource.cirrus.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Correct constant namingVitaly Rodionov
Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-5-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Remove unused struct members and constantsVitaly Rodionov
Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-4-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Sort #include directives and tydy up whitespacesVitaly Rodionov
Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-3-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: cs530x: Update the copyright headersVitaly Rodionov
Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://patch.msgid.link/20251023090327.58275-2-vitalyr@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: qcom: sm8250: add qrb2210-sndcard compatible stringAlexey Klimov
Add "qcom,qrb2210-sndcard" to the list of recognizable devices. Use "qcm2290" as name to let UCM to use it later. QRB2210 RB1 and other QCM2290-based boards can use this sndcard compatible. Cc: Srinivas Kandagatla <srini@kernel.org> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://patch.msgid.link/20251022-qrb2210-qcm2290-sndcard-v2-2-32e9e269a825@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27ASoC: dt-bindings: qcom,sm8250: add QRB2210 soundcardAlexey Klimov
Add soundcard compatible for QRB2210 (QCM2290) SoCs, where the older non-audioreach audio architecture is implemented. Cc: Srinivas Kandagatla <srini@kernel.org> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://patch.msgid.link/20251022-qrb2210-qcm2290-sndcard-v2-1-32e9e269a825@linaro.org Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-10-27clk: renesas: rzv2h: Add support for DSI clocksLad Prabhakar
Add support for PLLDSI and its post-dividers in the RZ/V2H CPG driver and export helper APIs for use by the DSI driver. Introduce per-PLL-DSI state in the CPG private structure and provide a set of helper functions that find valid PLL parameter combinations for a requested frequency. The new helpers are rzv2h_get_pll_pars(), rzv2h_get_pll_div_pars(), rzv2h_get_pll_divs_pars() and rzv2h_get_pll_dtable_pars() and they are exported in the "RZV2H_CPG" namespace for use by other consumers (notably the DSI driver). These helpers perform iterative searches over PLL parameters (M, K, P, S) and optional post-dividers and return the best match (or an exact match when possible). Move PLL/CLK related limits and parameter types into the shared include (include/linux/clk/renesas.h) by adding struct rzv2h_pll_limits, struct rzv2h_pll_pars and struct rzv2h_pll_div_pars plus the RZV2H_CPG_PLL_DSI_LIMITS() helper macro to define DSI PLL limits. This change centralises the PLLDSI algorithms so the CPG and DSI drivers compute PLL parameters consistently and allows the DSI driver to accurately request rates and program its PLL. Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251015192611.241920-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-27clk: renesas: rzv2h: Use GENMASK for PLL fieldsLad Prabhakar
Replace the older FIELD_GET-wrapping helper macros with plain GENMASK definitions for the PLL CLK1/CLK2 field masks (CPG_PLL_CLK1_KDIV, CPG_PLL_CLK1_MDIV, CPG_PLL_CLK1_PDIV and CPG_PLL_CLK2_SDIV). Update rzv2h_cpg_pll_clk_recalc_rate() to explicitly extract those fields with FIELD_GET and cast the KDIV extraction to s16 to ensure proper sign extension when computing the PLL output rate. Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251015192611.241920-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-27clk: renesas: rzv2h: Add instance field to struct pllLad Prabhakar
Add a two-bit "instance" member to struct pll and extend the PLL_PACK() macro to accept an instance parameter. Initialize all existing PLL definitions with instance 0 to preserve legacy behavior. This change enables support for SoCs with multiple PLL instances (for example, RZ/G3E we have two PLL DSIs). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251015192611.241920-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-27pinctrl: renesas: rzg2l: Remove useless wrappersCosmin Tanislav
rzg2l_gpio_irq_set_type() and rzg2l_gpio_irqc_eoi() only call the equivalent parent functions, replace their usage with the parent functions and remove them. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251022074100.1994447-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-10-27arm64: dts: mediatek: mt8365-evk: Enable GPU supportLouis-Alexis Eyraud
Enable for the Mediatek Genio 350-EVK board the support of the Arm Mali G52 MC1 GPU integrated in the MT8365 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-27arm64: dts: mediatek: mt8365: Add GPU supportLouis-Alexis Eyraud
The Mediatek MT8365 SoC has an integrated Arm Mali G52 MC1 GPU (Bifrost). Add gpu, OPP table, and MFG clock driver nodes in mt8365.dtsi to support it using the Panfrost driver. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-27arm64: dts: mediatek: mt8395-genio-1200-evk: Describe CPU suppliesNícolas F. R. A. Prado
The Genio 1200 EVK board has the big and little CPU clusters fed by the same regulators as MT8195-Cherry boards, so describe them in the same way as commit 17b33dd9e4a3 ("arm64: dts: mediatek: cherry: Describe CPU supplies"). This prevents the system from hanging during boot in the case that the cpufreq-mediatek-hw driver tries to probe before the drivers for the regulators have probed (which happens when using the current defconfig). Fixes: f2b543a191b6 ("arm64: dts: mediatek: add device-tree for Genio 1200 EVK board") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-10-27arm64: dts: ti: k3-am625: Add OLDI supportAradhya Bhatia
The AM625 SoC has 2 OLDI TXes under the DSS. Add their support. Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> Signed-off-by: Swamil Jain <s-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://patch.msgid.link/20250913064205.4152249-3-s-jain1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-10-27arm64: dts: ti: k3-am62: Add support for AM625 OLDI IO ControlAradhya Bhatia
Add TI DSS OLDI-IO control registers for AM625 DSS. This is a region of 12 32bit registers found in the TI AM625 CTRL_MMR0 register space[0]. They are used to control the characteristics of the OLDI DATA/CLK IO as needed by the DSS display controller node. [0]: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> Signed-off-by: Swamil Jain <s-jain1@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://patch.msgid.link/20250913064205.4152249-2-s-jain1@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-10-27RDMA/hns: Remove an extra blank lineGuofeng Yue
Remove an extra blank line. Signed-off-by: Guofeng Yue <yueguofeng@h-partners.com> Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://patch.msgid.link/20251016114051.1963197-5-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
2025-10-27RDMA/hns: Fix wrong WQE data when QP wraps aroundJunxian Huang
When QP wraps around, WQE data from the previous use at the same position still remains as driver does not clear it. The WQE field layout differs across different opcodes, causing that the fields that are not explicitly assigned for the current opcode retain stale values, and are issued to HW by mistake. Such fields are as follows: * MSG_START_SGE_IDX field in ATOMIC WQE * BLOCK_SIZE and ZBVA fields in FRMR WQE * DirectWQE fields when DirectWQE not used For ATOMIC WQE, always set the latest sge index in MSG_START_SGE_IDX as required by HW. For FRMR WQE and DirectWQE, clear only those unassigned fields instead of the entire WQE to avoid performance penalty. Fixes: 68a997c5d28c ("RDMA/hns: Add FRMR support for hip08") Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://patch.msgid.link/20251016114051.1963197-4-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
2025-10-27RDMA/hns: Fix the modification of max_send_sgewenglianfa
The actual sge number may exceed the value specified in init_attr->cap when HW needs extra sge to enable inline feature. Since these extra sges are not expected by ULP, return the user-specified value to ULP instead of the expanded sge number. Fixes: 0c5e259b06a8 ("RDMA/hns: Fix incorrect sge nums calculation") Signed-off-by: wenglianfa <wenglianfa@huawei.com> Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://patch.msgid.link/20251016114051.1963197-3-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
2025-10-27RDMA/hns: Fix recv CQ and QP cache affinityChengchang Tang
Currently driver enforces affinity between QP cache and send CQ cache, which helps improve the performance of sending, but doesn't set affinity with recv CQ cache, resulting in suboptimal performance of receiving. Use one CQ bank per context to ensure the affinity among QP, send CQ and recv CQ. For kernel ULP, CQ bank is fixed to 0. Fixes: 9e03dbea2b06 ("RDMA/hns: Fix CQ and QP cache affinity") Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://patch.msgid.link/20251016114051.1963197-2-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
2025-10-27xfrm: Skip redundant replay recheck for the hardware offload pathJianbo Liu
The xfrm_replay_recheck() function was introduced to handle the issues arising from asynchronous crypto algorithms. The crypto offload path is now effectively synchronous, as it holds the state lock throughout its operation. This eliminates the race condition, making the recheck an unnecessary overhead. This patch improves performance by skipping the redundant call when crypto_done is true. Additionally, the sequence number assignment is moved to an earlier point in the function. This improves performance by reducing lock contention and places the logic at a more appropriate point, as the full sequence number (including the higher-order bits) can be determined as soon as the packet is received. Signed-off-by: Jianbo Liu <jianbol@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
2025-10-27xfrm: Refactor xfrm_input lock to reduce contention with RSSJianbo Liu
With newer NICs like mlx5 supporting RSS for IPsec crypto offload, packets for a single Security Association (SA) are scattered across multiple CPU cores for parallel processing. The xfrm_state spinlock (x->lock) is held for each packet during xfrm processing. When multiple connections or flows share the same SA, this parallelism causes high lock contention on x->lock, creating a performance bottleneck and limiting scalability. The original xfrm_input() function exacerbated this issue by releasing and immediately re-acquiring x->lock. For hardware crypto offload paths, this unlock/relock sequence is unnecessary and introduces significant overhead. This patch refactors the function to relocate the type_offload->input_tail call for the offload path, performing all necessary work while continuously holding the lock. This reordering is safe, since packets which don't pass the checks below will still fail them with the new code. Performance testing with iperf using multiple parallel streams over a single IPsec SA shows significant improvement in throughput as the number of queues (and thus CPU cores) increases: +-----------+---------------+--------------+-----------------+ | RX queues | Before (Gbps) | After (Gbps) | Improvement (%) | +-----------+---------------+--------------+-----------------+ | 2 | 32.3 | 34.4 | 6.5 | | 4 | 34.4 | 40.0 | 16.3 | | 6 | 24.5 | 38.3 | 56.3 | | 8 | 23.1 | 38.3 | 65.8 | | 12 | 18.1 | 29.9 | 65.2 | | 16 | 16.0 | 25.2 | 57.5 | +-----------+---------------+--------------+-----------------+ Signed-off-by: Jianbo Liu <jianbol@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
2025-10-27gpio: qixis-fpga: Fix a NULL vs IS_ERR() bug in probe()Dan Carpenter
The devm_platform_ioremap_resource() function doesn't return NULL, it returns error pointers. Fix the checking to match. Fixes: e88500247dc3 ("gpio: add QIXIS FPGA GPIO controller") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/aPsaaf0h343Ba7c1@stanley.mountain Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-10-27ALSA: maestro3: using vmalloc_array() to handle the codetanze
Change array_size() to vmalloc_array(), due to vmalloc_array() being optimized better, using fewer instructions, and handles overflow more concisely. Signed-off-by: tanze <tanze@kylinos.cn> Link: https://patch.msgid.link/20251024105549.210654-1-tanze@kylinos.cn Signed-off-by: Takashi Iwai <tiwai@suse.de>
2025-10-27ALSA: usb-audio: don't log messages meant for 1810c when initializing 1824cRoy Vegard Ovesen
The log messages for the PreSonus STUDIO 1810c about device_setup are not applicable to the 1824c, and should not be logged when 1824c initializes. Refactor from if statement to switch statement as there might be more STUDIO series devices added later. Fixes: 080564558eb1 ("ALSA: usb-audio: enable support for Presonus Studio 1824c within 1810c file") Signed-off-by: Roy Vegard Ovesen <roy.vegard.ovesen@gmail.com> Link: https://patch.msgid.link/aPaYTP7ceuABf8c7@ark Signed-off-by: Takashi Iwai <tiwai@suse.de>
2025-10-27Merge tag 'v6.18-rc3' of ↵Bartosz Golaszewski
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next Linux 6.18-rc3
2025-10-27USB: serial: kobil_sct: drop unnecessary initialisationsJohan Hovold
Drop unnecessary initialisation of variables that are always assigned before being used. Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Johan Hovold <johan@kernel.org>
2025-10-27USB: serial: kobil_sct: clean up set_termios()Johan Hovold
Clean up set_termios() by using a shorter identifier for the control request value, replacing a ternary operator and adding some missing braces to make it more readable. Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Johan Hovold <johan@kernel.org>
2025-10-27USB: serial: kobil_sct: add control request helpersJohan Hovold
Refactor by adding two control request helpers to make the code more readable. Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Johan Hovold <johan@kernel.org>
2025-10-27USB: serial: kobil_sct: clean up device type checksJohan Hovold
Clean up the driver device type checks by moving logical operators to the previous line and using consistent indentation of continuation lines. Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Johan Hovold <johan@kernel.org>
2025-10-27USB: serial: kobil_sct: clean up tiocmset()Johan Hovold
Clean up the tiocmset() implementation by simplifying the flag check, dropping some dev_dbg(), logging errors using dev_err() and using a common control message call for both DTR and RTS to make the existing logic easier to follow. Note that the modem control lines are currently only manipulated in this function, which therefore does not require any locking. Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Johan Hovold <johan@kernel.org>
2025-10-27USB: serial: belkin_sa: clean up tiocmset()Johan Hovold
Clean up the tiocmset() implementation by dropping the dtr and rts flags to make the logic a little easier to follow. Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Johan Hovold <johan@kernel.org>
2025-10-27USB: serial: kobil_sct: fix TIOCMBIS and TIOCMBICJohan Hovold
Asserting or deasserting a modem control line using TIOCMBIS or TIOCMBIC should not deassert any lines that are not in the mask. Fix this long-standing issue dating back to 2003 when the support for these ioctls was added with the introduction of the tiocmset() callback. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Cc: stable@vger.kernel.org Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Johan Hovold <johan@kernel.org>
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