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2025-11-20phy: fsl-imx8mq-usb: support alternate reference clockXu Yang
This phy supports both 24MHz and 100MHz clock inputs. By default it's using XTAL 24MHz and the 100MHz clock is a alternate reference clock. Add supports to use alternate reference clock in case 24MHz clock can't work well. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://patch.msgid.link/20251118071947.2504789-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20dt-bindings: phy: imx8mq-usb: add alternate reference clockXu Yang
Beside default 24MHz clock input, there is an optional additional 100Mhz clock input 'alt' for USB PHY reference clock. Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://patch.msgid.link/20251118071947.2504789-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20sched_ext: tools: Removing duplicate targets during non-cross compilationRong Tao
When cross-compilation is not used, BPFOBJ and HOST_BPFOBJ are identical files, libbpf.a, and duplicate libbpf.a files should be removed. Signed-off-by: Rong Tao <rongtao@cestc.cn> Signed-off-by: Tejun Heo <tj@kernel.org>
2025-11-20phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limitsCristian Ciocaltea
Fixup PHY deskew FIFO to prevent the phase of D2 lane going ahead of other lanes. It's worth noting this might only happen when dealing with HDMI 2.0 rates. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-3-ecc642a59d94@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidthCristian Ciocaltea
Due to its relatively low frequency, a noise stemming from the 24MHz PLL reference clock may traverse the low-pass loop filter of ROPLL, which could potentially generate some HDMI flash artifacts. Reduce ROPLL loop bandwidth in an attempt to mitigate the problem. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Co-developed-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-2-ecc642a59d94@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc modeCristian Ciocaltea
When making use of the clock provider functionality, the output clock does normally match the TMDS character rate, which is what the PHY PLL gets configured to. However, this is only applicable for default color depth of 8 bpc. For higher depths, the output clock is further divided by the hardware according to the formula: output_clock_rate = tmds_char_rate * 8 / bpc Since the existence of the clock divider wasn't taken into account when support for high bpc has been introduced, make the necessary adjustments to report the correct clock rate. Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management") Reported-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-1-ecc642a59d94@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20sched/deadline: Walk up cpuset hierarchy to decide root domain when hot-unplugPingfan Liu
*** Bug description *** When testing kexec-reboot on a 144 cpus machine with isolcpus=managed_irq,domain,1-71,73-143 in kernel command line, I encounter the following bug: [ 97.114759] psci: CPU142 killed (polled 0 ms) [ 97.333236] Failed to offline CPU143 - error=-16 [ 97.333246] ------------[ cut here ]------------ [ 97.342682] kernel BUG at kernel/cpu.c:1569! [ 97.347049] Internal error: Oops - BUG: 00000000f2000800 [#1] SMP [...] In essence, the issue originates from the CPU hot-removal process, not limited to kexec. It can be reproduced by writing a SCHED_DEADLINE program that waits indefinitely on a semaphore, spawning multiple instances to ensure some run on CPU 72, and then offlining CPUs 1–143 one by one. When attempting this, CPU 143 failed to go offline. bash -c 'taskset -cp 0 $$ && for i in {1..143}; do echo 0 > /sys/devices/system/cpu/cpu$i/online 2>/dev/null; done' Tracking down this issue, I found that dl_bw_deactivate() returned -EBUSY, which caused sched_cpu_deactivate() to fail on the last CPU. But that is not the fact, and contributed by the following factors: When a CPU is inactive, cpu_rq()->rd is set to def_root_domain. For an blocked-state deadline task (in this case, "cppc_fie"), it was not migrated to CPU0, and its task_rq() information is stale. So its rq->rd points to def_root_domain instead of the one shared with CPU0. As a result, its bandwidth is wrongly accounted into a wrong root domain during domain rebuild. *** Issue *** The key point is that root_domain is only tracked through active rq->rd. To avoid using a global data structure to track all root_domains in the system, there should be a method to locate an active CPU within the corresponding root_domain. *** Solution *** To locate the active cpu, the following rules for deadline sub-system is useful -1.any cpu belongs to a unique root domain at a given time -2.DL bandwidth checker ensures that the root domain has active cpus. Now, let's examine the blocked-state task P. If P is attached to a cpuset that is a partition root, it is straightforward to find an active CPU. If P is attached to a cpuset that has changed from 'root' to 'member', the active CPUs are grouped into the parent root domain. Naturally, the CPUs' capacity and reserved DL bandwidth are taken into account in the ancestor root domain. (In practice, it may be unsafe to attach P to an arbitrary root domain, since that domain may lack sufficient DL bandwidth for P.) Again, it is straightforward to find an active CPU in the ancestor root domain. This patch groups CPUs into isolated and housekeeping sets. For the housekeeping group, it walks up the cpuset hierarchy to find active CPUs in P's root domain and retrieves the valid rd from cpu_rq(cpu)->rd. Signed-off-by: Pingfan Liu <piliu@redhat.com> Cc: Waiman Long <longman@redhat.com> Cc: Chen Ridong <chenridong@huaweicloud.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Juri Lelli <juri.lelli@redhat.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Ben Segall <bsegall@google.com> Cc: Mel Gorman <mgorman@suse.de> Cc: Valentin Schneider <vschneid@redhat.com> To: linux-kernel@vger.kernel.org Signed-off-by: Tejun Heo <tj@kernel.org>
2025-11-20cgroup/cpuset: Introduce cpuset_cpus_allowed_locked()Pingfan Liu
cpuset_cpus_allowed() uses a reader lock that is sleepable under RT, which means it cannot be called inside raw_spin_lock_t context. Introduce a new cpuset_cpus_allowed_locked() helper that performs the same function as cpuset_cpus_allowed() except that the caller must have acquired the cpuset_mutex so that no further locking will be needed. Suggested-by: Waiman Long <longman@redhat.com> Signed-off-by: Pingfan Liu <piliu@redhat.com> Cc: Waiman Long <longman@redhat.com> Cc: Tejun Heo <tj@kernel.org> Cc: Johannes Weiner <hannes@cmpxchg.org> Cc: Michal Koutný <mkoutny@suse.com> Cc: linux-kernel@vger.kernel.org To: cgroups@vger.kernel.org Reviewed-by: Chen Ridong <chenridong@huawei.com> Reviewed-by: Waiman Long <longman@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2025-11-20phy: ti: gmii-sel: Add a sanity check on the phy_idDan Carpenter
The "phy_id" comes from the device tree so it's going to be correct. But static checkers sometimes complain when we have an upper bounds check with no lower bounds check. Also it's a bit unusual that the lowest valid number is 1 instead of 0 so adding a check could potentially help someone. Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/aPJpB-QI8FMpFGOk@stanley.mountain Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20Merge tag 'net-6.18-rc7' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net Pull networking fixes from Jakub Kicinski: "Including fixes from IPsec and wireless. Previous releases - regressions: - prevent NULL deref in generic_hwtstamp_ioctl_lower(), newer APIs don't populate all the pointers in the request - phylink: add missing supported link modes for the fixed-link - mptcp: fix false positive warning in mptcp_pm_nl_rm_addr Previous releases - always broken: - openvswitch: remove never-working support for setting NSH fields - xfrm: number of fixes for error paths of xfrm_state creation/ modification/deletion - xfrm: fixes for offload - fix the determination of the protocol of the inner packet - don't push locally generated packets directly to L2 tunnel mode offloading, they still need processing from the standard xfrm path - mptcp: fix a couple of corner cases in fallback and fastclose handling - wifi: rtw89: hw_scan: prevent connections from getting stuck, work around apparent bug in FW by tweaking messages we send - af_unix: fix duplicate data if PEEK w/ peek_offset needs to wait - veth: more robust handing of race to avoid txq getting stuck - eth: ps3_gelic_net: handle skb allocation failures" * tag 'net-6.18-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (47 commits) vsock: Ignore signal/timeout on connect() if already established be2net: pass wrb_params in case of OS2BMC l2tp: reset skb control buffer on xmit net: dsa: microchip: lan937x: Fix RGMII delay tuning selftests: mptcp: add a check for 'add_addr_accepted' mptcp: fix address removal logic in mptcp_pm_nl_rm_addr selftests: mptcp: join: userspace: longer timeout selftests: mptcp: join: endpoints: longer timeout selftests: mptcp: join: fastclose: remove flaky marks mptcp: fix duplicate reset on fastclose mptcp: decouple mptcp fastclose from tcp close mptcp: do not fallback when OoO is present mptcp: fix premature close in case of fallback mptcp: avoid unneeded subflow-level drops mptcp: fix ack generation for fallback msk wifi: rtw89: hw_scan: Don't let the operating channel be last net: phylink: add missing supported link modes for the fixed-link selftest: af_unix: Add test for SO_PEEK_OFF. af_unix: Read sk_peek_offset() again after sleeping in unix_stream_read_generic(). net/mlx5: Clean up only new IRQ glue on request_irq() failure ...
2025-11-20phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHYPrudhvi Yarlagadda
Add support for Gen5 x4 PCIe QMP PHY found on Glymur platform. Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com> Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://patch.msgid.link/20251103-glymur-pcie-upstream-v6-3-18a5e0a538dc@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: qcom-qmp: pcs: Add v8.50 register offsetsPrudhvi Yarlagadda
The new Glymur SoC bumps up the HW version of QMP phy to v8.50 for PCIE g5x4. Add the new PCS offsets in a dedicated header file. Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com> Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://patch.msgid.link/20251103-glymur-pcie-upstream-v6-2-18a5e0a538dc@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHYPrudhvi Yarlagadda
The fifth PCIe instance on Glymur has a Gen5 4-lane PHY. Document it as a separate compatible. Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com> Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://patch.msgid.link/20251103-glymur-pcie-upstream-v6-1-18a5e0a538dc@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Restrict resets per each deviceKrzysztof Kozlowski
Bindings should be complete, thus complete the constraints for the resets by adding missing compatibles for devices with two resets and "else:" clause narrowing them for all other devices. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251017045919.34599-2-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: freescale: Initialize priv->lockXiaolei Wang
Initialize priv->lock to fix the following warning. WARNING: CPU: 0 PID: 12 at kernel/locking/mutex.c:577 __mutex_lock+0x70c/0x8b8 Modules linked in: Hardware name: Freescale i.MX8QM MEK (DT) Call trace: __mutex_lock+0x70c/0x8b8 (P) mutex_lock_nested+0x24/0x30 imx_hsio_power_on+0x4c/0x764 phy_power_on+0x7c/0x12c imx_pcie_host_init+0x1d0/0x4d4 dw_pcie_host_init+0x188/0x4b0 imx_pcie_probe+0x324/0x6f4 platform_probe+0x5c/0x98 really_probe+0xbc/0x29c __driver_probe_device+0x78/0x12c driver_probe_device+0xd8/0x160 __device_attach_driver+0xb8/0x138 bus_for_each_drv+0x84/0xe4 __device_attach_async_helper+0xb8/0xdc async_run_entry_fn+0x34/0xe0 process_one_work+0x220/0x694 worker_thread+0x1c0/0x36c kthread+0x14c/0x224 Fixes: 82c56b6dd24f ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support") Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20250925013806.569658-1-xiaolei.wang@windriver.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: renesas: Remove unneeded semicolonsGeert Uytterhoeven
Semicolons after end of function braces are not needed, remove them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/a8807dafa87fcc3abcafd34a1895e4c722c39793.1758719985.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLERonak Raheja
Certain platforms may not have the PHY_ENABLE bit set on power on reset. Update the current sequence to explicitly write to enable the PHY_ENABLE bit. This ensures that regardless of the platform, the PHY is properly enabled. Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20250920032158.242725-1-wesley.cheng@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: qcom: qmp-combo: get the USB3 & DisplayPort lanes mapping from DTNeil Armstrong
The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top of a combo glue to route either lanes to the 4 shared physical lanes. The routing of the lanes can be: - 2 DP + 2 USB3 - 4 DP - 2 USB3 Get the lanes mapping from DT and stop registering the USB-C muxes in favor of a static mode and orientation detemined by the lanes mapping. This allows supporting boards with direct connection of USB3 and DisplayPort lanes to the QMP Combo PHY lanes, not using the USB-C Altmode feature. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Xilin Wu <sophon@radxa.com> # qcs6490-radxa-dragon-q6a Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-topic-x1e80100-hdmi-v7-2-2bee0e66cc1b@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document lanes mapping when ↵Neil Armstrong
not using in USB-C complex The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top of a combo glue to route either lanes to the 4 shared physical lanes. The routing of the lanes can be: - 2 DP + 2 USB3 - 4 DP - 2 USB3 The layout of the lanes was designed to be mapped and swapped related to the USB-C Power Delivery negociation, so it supports a finite set of mappings inherited by the USB-C Altmode layouts. Nevertheless those QMP Comby PHY can be used to drive a DisplayPort connector, DP->HDMI bridge, USB3 A Connector, etc... without an USB-C connector and no PD events. Document the data-lanes on numbered port@0 out endpoints, allowing us to document the lanes mapping to DisplayPort and/or USB3 connectors/peripherals. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-topic-x1e80100-hdmi-v7-1-2bee0e66cc1b@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562Shawn Lin
When PCIe link enters L1 PM substates, the PHY will turn off its PLL for power-saving. However, it turns off the PLL too fast which leads the PHY to be broken. According to the PHY document, we need to delay PLL turnoff time. Fixes: f13bff25161b ("phy: rockchip-naneng-combo: Support rk3562") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/1763459526-35004-2-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528Shawn Lin
When PCIe link enters L1 PM substates, the PHY will turn off its PLL for power-saving. However, it turns off the PLL too fast which leads the PHY to be broken. According to the PHY document, we need to delay PLL turnoff time. Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/1763459526-35004-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: renesas: rcar-gen3-usb2: Add suspend/resume supportClaudiu Beznea
The Renesas RZ/G3S supports a power saving mode where power to most of the SoC components is turned off. The USB PHY is among these components. Because of this the settings applied in driver probe need to be executed also on resume path. On suspend path only reset signal need to be asserted. Add suspend/resume support. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119120418.686224-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: renesas: rcar-gen3-usb2: Move phy_data->init_bus checkClaudiu Beznea
Move the check of phy_data->init_bus from rcar_gen3_phy_usb2_init_bus() to rcar_gen3_phy_usb2_probe() to avoid having it duplicated in both the probe path and the upcoming resume code. This is a preparatory patch. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119120418.686224-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: renesas: rcar-gen3-usb2: Fix an error handling path in ↵Christophe JAILLET
rcar_gen3_phy_usb2_probe() If an error occurs after the reset_control_deassert(), reset_control_assert() must be called, as already done in the remove function. Use devm_add_action_or_reset() to add the missing call and simplify the .remove() function accordingly. While at it, drop struct rcar_gen3_chan::rstc as it is not used aymore. [claudiu.beznea: removed "struct reset_control *rstc = data;" from rcar_gen3_reset_assert(), dropped struct rcar_gen3_chan::rstc] Fixes: 4eae16375357 ("phy: renesas: rcar-gen3-usb2: Add support to initialize the bus") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20251023135810.1688415-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3SClaudiu Beznea
The reset lines are mandatory for the Renesas RZ/G3S platform and must be explicitly defined in device tree. Fixes: f3c849855114 ("dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings") Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20251023135810.1688415-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: exynos5-usbdrd: fix clock prepare imbalanceAndré Draszik
Commit f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)") incorrectly added clk_bulk_disable() as the inverse of clk_bulk_prepare_enable() while it should have of course used clk_bulk_disable_unprepare(). This means incorrect reference counts to the CMU driver remain. Update the code accordingly. Fixes: f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)") CC: stable@vger.kernel.org Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20251006-gs101-usb-phy-clk-imbalance-v1-1-205b206126cf@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20firmware: cs_dsp: Cleanup debugfs for wmfw and binMark Brown
Merge series from Richard Fitzgerald <rf@opensource.cirrus.com>: These two patches improve the implementation of the debugfs files for the wmfw and bin file names. First patch removes duplicated code. Second patch replaces the old clunkiness of storing the filename with an appended \n. The \n can be appended when the file is read, to keep the stored string sane.
2025-11-20phy: broadcom: bcm63xx-usbh: fix section mismatchesJohan Hovold
Platform drivers can be probed after their init sections have been discarded (e.g. on probe deferral or manual rebind through sysfs) so the probe function and match table must not live in init. Fixes: 783f6d3dcf35 ("phy: bcm63xx-usbh: Add BCM63xx USBH driver") Cc: stable@vger.kernel.org # 5.9 Cc: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Johan Hovold <johan@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251017054537.6884-1-johan@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: rockchip: inno-dsidphy: Add support for rk3506Chaoyi Chen
For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes and a maximum data rate of 1.5GHz. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251106020632.92-7-kernel@airkyi.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20dt-bindings: phy: rockchip-inno-dsidphy: Add compatible for rk3506Chaoyi Chen
Document a compatible string for the rk3506 dsi-dphy. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251106020632.92-3-kernel@airkyi.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20regulator: Add FP9931/JD9930 driverAndreas Kemnade
Add a driver for the FP9931/JD9930 regulator. Implement handling of the PG (power good), TS_EN (temperature sensor enable), and EN (enable regulators) pins. Implement the pair of symmetric LDOs as a single regulator because they share a single voltage set register. For simplicity, just add the temperature sensor (depending on external NTC) directly. Limitations: - As these regulators are controlled together with the VCOM regulator via the EN pin, some kind of management must be in place. As the enable op is not called when the regulator is already enabled, simple refcounting seems not to work to avoid clearing EN when one regulator is still enabled. As these regulators are typically used together, this limitation should not hurt hard, just provide the is_enabled op. - As the VCOM step is quite odd (5V/255 steps), rounding is needed. Due to some limitations in the regulator core, the max/min voltages in the devicetree must match the idea of the driver how to round things exactly. - Night mode is not implemented, so only the FP9931 compatible is needed in the driver, there is no REGULATOR_MODE_NIGHT and no clear definition in the datasheet what it does, also the XON pin which seems to be an input related to that night mode is not used. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://patch.msgid.link/20251115-fp9931-submit-v3-3-92f5d0772b68@kemnade.info Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-20dt-bindings: regulator: Add Fitipower FP9931/JD9930Andreas Kemnade
Document the FP9931/JD9930. As the FP9931 is a clear subset of the JD9930, define it as a fallback compatible. GPIO names are same as in the datasheet except for the EN pad which is described as "enable". Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://patch.msgid.link/20251115-fp9931-submit-v3-2-92f5d0772b68@kemnade.info Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-20dt-bindings: vendor-prefixes: Add FitipowerAndreas Kemnade
Add Fitipower Integrated Technology Inc. to the vendor prefixes. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://patch.msgid.link/20251115-fp9931-submit-v3-1-92f5d0772b68@kemnade.info Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-20ASoC: renesas: rz-ssi: Fix rz_ssi_priv::hw_params_cache::sample_widthBiju Das
The strm->sample_width is not filled during rz_ssi_dai_hw_params(). This wrong value is used for caching sample_width in struct hw_params_cache. Fix this issue by replacing 'strm->sample_width'->'params_width(params)' in rz_ssi_dai_hw_params(). After this drop the variable sample_width from struct rz_ssi_stream as it is unused. Cc: stable@kernel.org Fixes: 4f8cd05a4305 ("ASoC: sh: rz-ssi: Add full duplex support") Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20251114073709.4376-3-biju.das.jz@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-20ASoC: renesas: rz-ssi: Fix channel swap issue in full duplex modeBiju Das
The full duplex audio starts with half duplex mode and then switch to full duplex mode (another FIFO reset) when both playback/capture streams available leading to random audio left/right channel swap issue. Fix this channel swap issue by detecting the full duplex condition by populating struct dup variable in startup() callback and synchronize starting both the play and capture at the same time in rz_ssi_start(). Cc: stable@kernel.org Fixes: 4f8cd05a4305 ("ASoC: sh: rz-ssi: Add full duplex support") Co-developed-by: Tony Tang <tony.tang.ks@renesas.com> Signed-off-by: Tony Tang <tony.tang.ks@renesas.com> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20251114073709.4376-2-biju.das.jz@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-20dt-bindings: phy: mediatek,tphy: Add support for MT7981Sjoerd Simons
Add a compatible string for Filogic 820, this chip integrates a MediaTek generic T-PHY version 2 Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Link: https://patch.msgid.link/20251115-openwrt-one-network-v4-3-48cbda2969ac@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20ASoC: cs35l56: Use SND_SOC_BYTES_E_ACC() for CAL_DATA_RB controlRichard Fitzgerald
Use the new SND_SOC_BYTES_E_ACC() macro instead of SND_SOC_BYTES_E() to define the CAL_DATA_RB control, so that it is marked as read-only and volatile. This avoids userland code expecting to be able to write to it and then getting an unexpected EPERM error, or assuming that its value can never change. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://patch.msgid.link/20251120134437.1179191-5-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-20ASoC: cs35l56: Use SOC_ENUM_EXT_ACC() for CAL_SET_STATUS controlRichard Fitzgerald
Use the new SOC_ENUM_EXT_ACC() macro instead of SOC_ENUM_EXT() to define the CAL_SET_STATUS control, so that it is marked as read-only and volatile. This avoids userland code expecting to be able to write to it and then getting an unexpected EPERM error, or assuming that its value can never change. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://patch.msgid.link/20251120134437.1179191-4-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-20ASoC: soc.h: Add SND_SOC_BYTES_E_ACC() to allow setting access flagsRichard Fitzgerald
Add a macro SND_SOC_BYTES_E_ACC() to allow the access permission flags to be set. This is the same as SND_SOC_BYTES_E() but with an extra argument for the access flags. This will be used by the cs35l56.c driver to create a read-only volatile byte control. It's preferable to avoid custom control macros in codec drivers. Code maintenance is easier if all control macros are defined together in soc.h. This commit only creates this one macro that is actually going to be used. There's no point cluttering soc.h with unused macros - that just adds a maintenance burden. People can add equivalents for the other macros if they need them. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://patch.msgid.link/20251120134437.1179191-3-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-20ASoC: soc.h: Add SOC_ENUM_EXT_ACC() to allow setting access flagsRichard Fitzgerald
Add a macro SOC_ENUM_EXT_ACC() to allow the access permission flags to be set. This is the same as SOC_ENUM_EXT() but with an extra argument for the access flags. This will be used by the cs35l56.c driver to create a read-only volatile enum. It's preferable to avoid custom control macros in codec drivers. Code maintenance is easier if all control macros are defined together in soc.h. This commit only creates this one macro that is actually going to be used. There's no point cluttering soc.h with unused macros - that just adds a maintenance burden. People can add equivalents for the other macros if they need them. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://patch.msgid.link/20251120134437.1179191-2-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-20reset: gpio: use software nodes to setup the GPIO lookupBartosz Golaszewski
GPIO machine lookup is a nice mechanism for associating GPIOs with consumers if we don't know what kind of device the GPIO provider is or when it will become available. However in the case of the reset-gpio, we are already holding a reference to the device and so can reference its firmware node. Let's setup a software node that references the relevant GPIO and attach it to the auxiliary device we're creating. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-11-20reset: gpio: convert the driver to using the auxiliary busBartosz Golaszewski
As the reset-gpio devices are purely virtual and never instantiated from real firmware nodes, let's convert the driver to using the - more fitting - auxiliary bus. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-11-20reset: make the provider of reset-gpios the parent of the reset deviceBartosz Golaszewski
Auxiliary devices really do need a parent so ahead of converting the reset-gpios driver to registering on the auxiliary bus, make the GPIO device that provides the reset GPIO the parent of the reset-gpio device. To that end move the lookup of the GPIO device by fwnode to the beginning of __reset_add_reset_gpio_device() which has the added benefit of bailing out earlier, before allocating resources for the virtual device, if the chip is not up yet. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-11-20reset: order includes alphabetically in reset/core.cBartosz Golaszewski
For better readability and easier maintenance order the includes alphabetically. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-11-20gpio: swnode: allow referencing GPIO chips by firmware nodesBartosz Golaszewski
When doing a software node lookup, we require both the fwnode that references a GPIO chip as well as the node associated with that chip to be software nodes. However, we now allow referencing generic firmware nodes from software nodes in driver core so we should allow the same in GPIO core. Make the software node name check optional and dependent on whether the referenced firmware node is a software node. If it's not, just continue with the lookup. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-11-20spi: cs42l43: Use actual ACPI firmware node for chip selectsCharles Keepax
On some systems the cs42l43 has amplifiers attached to its SPI controller that are not properly defined in ACPI. Currently software nodes are added to support this case, however, the chip selects for these devices are specified using a hack. A software node is added with the same name as the pinctrl driver, as the look up was name based, this allowed the GPIO look up to return the pinctrl driver even though the swnode was not owned by it. This was necessary as the swnodes did not support directly linking to real firmware nodes. Since commit e5d527be7e69 ("gpio: swnode: don't use the swnode's name as the key for GPIO lookup") changed the lookup to be fwnode based this hack will no longer find the pinctrl driver, resulting in the driver not probing. There is no pinctrl driver attached to the swnode itself. But other patches did add support for linking a swnode to a real fwnode node [1]. As such the hack is no longer needed, so switch over to just passing the real fwnode for the pinctrl property to avoid any issues. [Bartosz: - remove unneeded Fixes: tag, - use PROPERTY_ENTRY_REF_ARRAY() instead of PROPERTY_ENTRY_REF_ARRAY_LEN()] Link: https://lore.kernel.org/linux-gpio/20251106-reset-gpios-swnodes-v6-0-69aa852de9e4@linaro.org/ [1] Fixes: 439fbc97502a ("spi: cs42l43: Add bridged cs35l56 amplifiers") Cc: stable+noautosel@kernel.org # Don't backport, previous approach works, fix relies on swnode changes Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-11-20software node: allow referencing firmware nodesBartosz Golaszewski
At the moment software nodes can only reference other software nodes. This is a limitation for devices created, for instance, on the auxiliary bus with a dynamic software node attached which cannot reference devices the firmware node of which is "real" (as an OF node or otherwise). Make it possible for a software node to reference all firmware nodes in addition to static software nodes. To that end: add a second pointer to struct software_node_ref_args of type struct fwnode_handle. The core swnode code will first check the swnode pointer and if it's NULL, it will assume the fwnode pointer should be set. Software node graphs remain the same, as in: the remote endpoints still have to be software nodes. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Tested-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-11-20software node: increase the reference of the swnode by its fwnodeBartosz Golaszewski
Once we allow software nodes to reference other kinds of firmware nodes, the node in args will no longer necessarily be a software node so bump its reference count using its fwnode interface. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Tested-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-11-20software node: read the reference args via the fwnode APIBartosz Golaszewski
Once we allow software nodes to reference all kinds of firmware nodes, the refnode here will no longer necessarily be a software node so read its proprties going through its fwnode implementation. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-11-20HID: bpf: fix typo in HID usage tableBenjamin Tissoires
We could go to the USB consortium, but it's probably easier that way. And update HID usage table json generated file from https://usb.org/sites/default/files/hut1_6.pdf updated: 01/30/2025 Reported-by: Colin Ian King <colin.i.king@gmail.com> Link: https://gitlab.freedesktop.org/libevdev/udev-hid-bpf/-/merge_requests/191 Signed-off-by: Benjamin Tissoires <benjamin.tissoires@gmail.com> Signed-off-by: Benjamin Tissoires <bentiss@kernel.org> Signed-off-by: Jiri Kosina <jkosina@suse.com>