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path: root/drivers/i2c/busses/i2c-tegra.c
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Diffstat (limited to 'drivers/i2c/busses/i2c-tegra.c')
-rw-r--r--drivers/i2c/busses/i2c-tegra.c306
1 files changed, 258 insertions, 48 deletions
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index e533460bccc3..bec619b9af4e 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -85,6 +85,7 @@
#define PACKET_HEADER0_PROTOCOL GENMASK(7, 4)
#define PACKET_HEADER0_PROTOCOL_I2C 1
+#define I2C_HEADER_HS_MODE BIT(22)
#define I2C_HEADER_CONT_ON_NAK BIT(21)
#define I2C_HEADER_READ BIT(19)
#define I2C_HEADER_10BIT_ADDR BIT(18)
@@ -136,6 +137,14 @@
#define I2C_MASTER_RESET_CNTRL 0x0a8
+#define I2C_SW_MUTEX 0x0ec
+#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0)
+#define I2C_SW_MUTEX_GRANT GENMASK(7, 4)
+#define I2C_SW_MUTEX_ID_CCPLEX 9
+
+/* SW mutex acquire timeout value in microseconds. */
+#define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC)
+
/* configuration load timeout in microseconds */
#define I2C_CONFIG_LOAD_TIMEOUT 1000000
@@ -196,16 +205,24 @@ enum msg_end_type {
* @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
* @tlow_std_mode: Low period of the clock in standard mode.
* @thigh_std_mode: High period of the clock in standard mode.
- * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
- * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
+ * @tlow_fast_mode: Low period of the clock in fast mode.
+ * @thigh_fast_mode: High period of the clock in fast mode.
+ * @tlow_fastplus_mode: Low period of the clock in fast-plus mode.
+ * @thigh_fastplus_mode: High period of the clock in fast-plus mode.
+ * @tlow_hs_mode: Low period of the clock in HS mode.
+ * @thigh_hs_mode: High period of the clock in HS mode.
* @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
* in standard mode.
- * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
- * conditions in fast/fast-plus modes.
+ * @setup_hold_time_fast_mode: Setup and hold time for start and stop
+ * conditions in fast mode.
+ * @setup_hold_time_fastplus_mode: Setup and hold time for start and stop
+ * conditions in fast-plus mode.
* @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
* in HS mode.
* @has_interface_timing_reg: Has interface timing register to program the tuned
* timing settings.
+ * @enable_hs_mode_support: Enable support for high speed (HS) mode transfers.
+ * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs.
*/
struct tegra_i2c_hw_feature {
bool has_continue_xfer_support;
@@ -224,12 +241,19 @@ struct tegra_i2c_hw_feature {
bool has_apb_dma;
u32 tlow_std_mode;
u32 thigh_std_mode;
- u32 tlow_fast_fastplus_mode;
- u32 thigh_fast_fastplus_mode;
+ u32 tlow_fast_mode;
+ u32 thigh_fast_mode;
+ u32 tlow_fastplus_mode;
+ u32 thigh_fastplus_mode;
+ u32 tlow_hs_mode;
+ u32 thigh_hs_mode;
u32 setup_hold_time_std_mode;
- u32 setup_hold_time_fast_fast_plus_mode;
+ u32 setup_hold_time_fast_mode;
+ u32 setup_hold_time_fastplus_mode;
u32 setup_hold_time_hs_mode;
bool has_interface_timing_reg;
+ bool enable_hs_mode_support;
+ bool has_mutex;
};
/**
@@ -240,7 +264,6 @@ struct tegra_i2c_hw_feature {
* @div_clk: clock reference for div clock of I2C controller
* @clocks: array of I2C controller clocks
* @nclocks: number of clocks in the array
- * @rst: reset control for the I2C controller
* @base: ioremapped registers cookie
* @base_phys: physical base address of the I2C controller
* @cont_id: I2C controller ID, used for packet header
@@ -269,7 +292,6 @@ struct tegra_i2c_dev {
struct i2c_adapter adapter;
const struct tegra_i2c_hw_feature *hw;
- struct reset_control *rst;
unsigned int cont_id;
unsigned int irq;
@@ -374,6 +396,76 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
}
+static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev)
+{
+ unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
+ u32 val, id;
+
+ val = readl(i2c_dev->base + reg);
+ id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
+
+ return id == I2C_SW_MUTEX_ID_CCPLEX;
+}
+
+static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev)
+{
+ unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
+ u32 val, id;
+
+ val = readl(i2c_dev->base + reg);
+ id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
+ if (id != 0 && id != I2C_SW_MUTEX_ID_CCPLEX)
+ return false;
+
+ val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX);
+ writel(val, i2c_dev->base + reg);
+
+ return tegra_i2c_mutex_acquired(i2c_dev);
+}
+
+static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev)
+{
+ bool locked;
+ int ret;
+
+ if (!i2c_dev->hw->has_mutex)
+ return 0;
+
+ if (i2c_dev->atomic_mode)
+ ret = read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked,
+ USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US,
+ false, i2c_dev);
+ else
+ ret = read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_PER_MSEC,
+ I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev);
+
+ if (ret)
+ dev_warn(i2c_dev->dev, "failed to acquire mutex\n");
+
+ return ret;
+}
+
+static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev)
+{
+ unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
+ u32 val, id;
+
+ if (!i2c_dev->hw->has_mutex)
+ return 0;
+
+ val = readl(i2c_dev->base + reg);
+
+ id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
+ if (id && id != I2C_SW_MUTEX_ID_CCPLEX) {
+ dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n", id);
+ return -EPERM;
+ }
+
+ writel(0, i2c_dev->base + reg);
+
+ return 0;
+}
+
static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
{
u32 int_mask;
@@ -449,6 +541,11 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
if (IS_VI(i2c_dev))
return 0;
+ if (!of_property_present(i2c_dev->dev->of_node, "dmas")) {
+ dev_dbg(i2c_dev->dev, "DMA not available, falling back to PIO\n");
+ return 0;
+ }
+
if (i2c_dev->hw->has_apb_dma) {
if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n");
@@ -634,6 +731,7 @@ static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev)
static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
{
u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
+ u32 max_bus_freq_hz;
struct i2c_timings *t = &i2c_dev->timings;
int err;
@@ -672,25 +770,40 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
if (IS_VI(i2c_dev))
tegra_i2c_vi_init(i2c_dev);
- switch (t->bus_freq_hz) {
- case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
- default:
- tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
- thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
- tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
+ if (i2c_dev->hw->enable_hs_mode_support)
+ max_bus_freq_hz = I2C_MAX_HIGH_SPEED_MODE_FREQ;
+ else
+ max_bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
- if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
- non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
- else
- non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
- break;
+ if (WARN_ON(t->bus_freq_hz > max_bus_freq_hz))
+ t->bus_freq_hz = max_bus_freq_hz;
- case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
+ if (t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
tlow = i2c_dev->hw->tlow_std_mode;
thigh = i2c_dev->hw->thigh_std_mode;
tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
- break;
+ } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
+ tlow = i2c_dev->hw->tlow_fast_mode;
+ thigh = i2c_dev->hw->thigh_fast_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
+ non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
+ } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
+ tlow = i2c_dev->hw->tlow_fastplus_mode;
+ thigh = i2c_dev->hw->thigh_fastplus_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_fastplus_mode;
+ non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
+ } else {
+ /*
+ * When using HS mode, i.e. when the bus frequency is greater than fast plus mode,
+ * the non-hs timing registers will be used for sending the master code byte for
+ * transition to HS mode. Configure the non-hs timing registers for Fast Mode to
+ * send the master code byte at 400kHz.
+ */
+ tlow = i2c_dev->hw->tlow_fast_mode;
+ thigh = i2c_dev->hw->thigh_fast_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
+ non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
}
/* make sure clock divisor programmed correctly */
@@ -712,6 +825,18 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
+ /* Write HS mode registers. These will get used only for HS mode*/
+ if (i2c_dev->hw->enable_hs_mode_support) {
+ tlow = i2c_dev->hw->tlow_hs_mode;
+ thigh = i2c_dev->hw->thigh_hs_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode;
+
+ val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) |
+ FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow);
+ i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0);
+ i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1);
+ }
+
clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
err = clk_set_rate(i2c_dev->div_clk,
@@ -1209,6 +1334,9 @@ static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
if (msg->flags & I2C_M_RD)
packet_header |= I2C_HEADER_READ;
+ if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
+ packet_header |= I2C_HEADER_HS_MODE;
+
if (i2c_dev->dma_mode && !i2c_dev->msg_read)
*dma_buf++ = packet_header;
else
@@ -1393,6 +1521,10 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
return ret;
}
+ ret = tegra_i2c_mutex_lock(i2c_dev);
+ if (ret)
+ return ret;
+
for (i = 0; i < num; i++) {
enum msg_end_type end_type = MSG_END_STOP;
@@ -1422,6 +1554,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
break;
}
+ ret = tegra_i2c_mutex_unlock(i2c_dev);
pm_runtime_put(i2c_dev->dev);
return ret ?: i;
@@ -1491,12 +1624,17 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
.has_apb_dma = true,
.tlow_std_mode = 0x4,
.thigh_std_mode = 0x2,
- .tlow_fast_fastplus_mode = 0x4,
- .thigh_fast_fastplus_mode = 0x2,
+ .tlow_fast_mode = 0x4,
+ .thigh_fast_mode = 0x2,
+ .tlow_fastplus_mode = 0x4,
+ .thigh_fastplus_mode = 0x2,
.setup_hold_time_std_mode = 0x0,
- .setup_hold_time_fast_fast_plus_mode = 0x0,
+ .setup_hold_time_fast_mode = 0x0,
+ .setup_hold_time_fastplus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = false,
+ .enable_hs_mode_support = false,
+ .has_mutex = false,
};
static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
@@ -1516,12 +1654,17 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
.has_apb_dma = true,
.tlow_std_mode = 0x4,
.thigh_std_mode = 0x2,
- .tlow_fast_fastplus_mode = 0x4,
- .thigh_fast_fastplus_mode = 0x2,
+ .tlow_fast_mode = 0x4,
+ .thigh_fast_mode = 0x2,
+ .tlow_fastplus_mode = 0x4,
+ .thigh_fastplus_mode = 0x2,
.setup_hold_time_std_mode = 0x0,
- .setup_hold_time_fast_fast_plus_mode = 0x0,
+ .setup_hold_time_fast_mode = 0x0,
+ .setup_hold_time_fastplus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = false,
+ .enable_hs_mode_support = false,
+ .has_mutex = false,
};
static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
@@ -1541,12 +1684,17 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
.has_apb_dma = true,
.tlow_std_mode = 0x4,
.thigh_std_mode = 0x2,
- .tlow_fast_fastplus_mode = 0x4,
- .thigh_fast_fastplus_mode = 0x2,
+ .tlow_fast_mode = 0x4,
+ .thigh_fast_mode = 0x2,
+ .tlow_fastplus_mode = 0x4,
+ .thigh_fastplus_mode = 0x2,
.setup_hold_time_std_mode = 0x0,
- .setup_hold_time_fast_fast_plus_mode = 0x0,
+ .setup_hold_time_fast_mode = 0x0,
+ .setup_hold_time_fastplus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = false,
+ .enable_hs_mode_support = false,
+ .has_mutex = false,
};
static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
@@ -1566,12 +1714,17 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
.has_apb_dma = true,
.tlow_std_mode = 0x4,
.thigh_std_mode = 0x2,
- .tlow_fast_fastplus_mode = 0x4,
- .thigh_fast_fastplus_mode = 0x2,
+ .tlow_fast_mode = 0x4,
+ .thigh_fast_mode = 0x2,
+ .tlow_fastplus_mode = 0x4,
+ .thigh_fastplus_mode = 0x2,
.setup_hold_time_std_mode = 0x0,
- .setup_hold_time_fast_fast_plus_mode = 0x0,
+ .setup_hold_time_fast_mode = 0x0,
+ .setup_hold_time_fastplus_mode = 0x0,
.setup_hold_time_hs_mode = 0x0,
.has_interface_timing_reg = true,
+ .enable_hs_mode_support = false,
+ .has_mutex = false,
};
static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
@@ -1591,12 +1744,17 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
.has_apb_dma = true,
.tlow_std_mode = 0x4,
.thigh_std_mode = 0x2,
- .tlow_fast_fastplus_mode = 0x4,
- .thigh_fast_fastplus_mode = 0x2,
+ .tlow_fast_mode = 0x4,
+ .thigh_fast_mode = 0x2,
+ .tlow_fastplus_mode = 0x4,
+ .thigh_fastplus_mode = 0x2,
.setup_hold_time_std_mode = 0,
- .setup_hold_time_fast_fast_plus_mode = 0,
+ .setup_hold_time_fast_mode = 0,
+ .setup_hold_time_fastplus_mode = 0,
.setup_hold_time_hs_mode = 0,
.has_interface_timing_reg = true,
+ .enable_hs_mode_support = false,
+ .has_mutex = false,
};
static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
@@ -1616,12 +1774,17 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
.has_apb_dma = false,
.tlow_std_mode = 0x4,
.thigh_std_mode = 0x3,
- .tlow_fast_fastplus_mode = 0x4,
- .thigh_fast_fastplus_mode = 0x2,
+ .tlow_fast_mode = 0x4,
+ .thigh_fast_mode = 0x2,
+ .tlow_fastplus_mode = 0x4,
+ .thigh_fastplus_mode = 0x2,
.setup_hold_time_std_mode = 0,
- .setup_hold_time_fast_fast_plus_mode = 0,
+ .setup_hold_time_fast_mode = 0,
+ .setup_hold_time_fastplus_mode = 0,
.setup_hold_time_hs_mode = 0,
.has_interface_timing_reg = true,
+ .enable_hs_mode_support = false,
+ .has_mutex = false,
};
static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
@@ -1641,21 +1804,60 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
.has_apb_dma = false,
.tlow_std_mode = 0x8,
.thigh_std_mode = 0x7,
- .tlow_fast_fastplus_mode = 0x2,
- .thigh_fast_fastplus_mode = 0x2,
+ .tlow_fast_mode = 0x2,
+ .thigh_fast_mode = 0x2,
+ .tlow_fastplus_mode = 0x2,
+ .thigh_fastplus_mode = 0x2,
+ .tlow_hs_mode = 0x8,
+ .thigh_hs_mode = 0x3,
.setup_hold_time_std_mode = 0x08080808,
- .setup_hold_time_fast_fast_plus_mode = 0x02020202,
+ .setup_hold_time_fast_mode = 0x02020202,
+ .setup_hold_time_fastplus_mode = 0x02020202,
.setup_hold_time_hs_mode = 0x090909,
.has_interface_timing_reg = true,
+ .enable_hs_mode_support = true,
+ .has_mutex = false,
};
static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
.has_continue_xfer_support = true,
.has_per_pkt_xfer_complete_irq = true,
- .clk_divisor_hs_mode = 7,
+ .clk_divisor_hs_mode = 9,
.clk_divisor_std_mode = 0x7a,
.clk_divisor_fast_mode = 0x40,
- .clk_divisor_fast_plus_mode = 0x19,
+ .clk_divisor_fast_plus_mode = 0x14,
+ .has_config_load_reg = true,
+ .has_multi_master_mode = true,
+ .has_slcg_override_reg = true,
+ .has_mst_fifo = true,
+ .has_mst_reset = true,
+ .quirks = &tegra194_i2c_quirks,
+ .supports_bus_clear = true,
+ .has_apb_dma = false,
+ .tlow_std_mode = 0x8,
+ .thigh_std_mode = 0x7,
+ .tlow_fast_mode = 0x4,
+ .thigh_fast_mode = 0x2,
+ .tlow_fastplus_mode = 0x4,
+ .thigh_fastplus_mode = 0x4,
+ .tlow_hs_mode = 0x3,
+ .thigh_hs_mode = 0x2,
+ .setup_hold_time_std_mode = 0x08080808,
+ .setup_hold_time_fast_mode = 0x04010101,
+ .setup_hold_time_fastplus_mode = 0x04020202,
+ .setup_hold_time_hs_mode = 0x030303,
+ .has_interface_timing_reg = true,
+ .enable_hs_mode_support = true,
+ .has_mutex = true,
+};
+
+static const struct tegra_i2c_hw_feature tegra264_i2c_hw = {
+ .has_continue_xfer_support = true,
+ .has_per_pkt_xfer_complete_irq = true,
+ .clk_divisor_hs_mode = 1,
+ .clk_divisor_std_mode = 0x1d,
+ .clk_divisor_fast_mode = 0x15,
+ .clk_divisor_fast_plus_mode = 0x8,
.has_config_load_reg = true,
.has_multi_master_mode = true,
.has_slcg_override_reg = true,
@@ -1666,15 +1868,23 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
.has_apb_dma = false,
.tlow_std_mode = 0x8,
.thigh_std_mode = 0x7,
- .tlow_fast_fastplus_mode = 0x3,
- .thigh_fast_fastplus_mode = 0x3,
+ .tlow_fast_mode = 0x2,
+ .thigh_fast_mode = 0x2,
+ .tlow_fastplus_mode = 0x2,
+ .thigh_fastplus_mode = 0x2,
+ .tlow_hs_mode = 0x4,
+ .thigh_hs_mode = 0x2,
.setup_hold_time_std_mode = 0x08080808,
- .setup_hold_time_fast_fast_plus_mode = 0x02020202,
+ .setup_hold_time_fast_mode = 0x02020202,
+ .setup_hold_time_fastplus_mode = 0x02020202,
.setup_hold_time_hs_mode = 0x090909,
.has_interface_timing_reg = true,
+ .enable_hs_mode_support = true,
+ .has_mutex = true,
};
static const struct of_device_id tegra_i2c_of_match[] = {
+ { .compatible = "nvidia,tegra264-i2c", .data = &tegra264_i2c_hw, },
{ .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },
{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
generated by cgit v1.2.3 (git 2.25.1) at 2026-08-05 14:38:30 +0000