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path: root/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h16
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
index 4586a425dbe4..4ec0a3a21169 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
@@ -4,6 +4,17 @@
#include <core/memory.h>
enum nvkm_memory_target;
+union nvkm_pte_tracker {
+ u32 u;
+ struct {
+ u32 sparse:1;
+ u32 spte_valid:1;
+ u32 lpte_valid:1;
+ u32 lptes:13;
+ u32 sptes:16;
+ } s;
+};
+
struct nvkm_vmm_pt {
/* Some GPUs have a mapping level with a dual page tables to
* support large and small pages in the same address-range.
@@ -44,10 +55,7 @@ struct nvkm_vmm_pt {
*
* This information is used to manage LPTE state transitions.
*/
-#define NVKM_VMM_PTE_SPARSE 0x80
-#define NVKM_VMM_PTE_VALID 0x40
-#define NVKM_VMM_PTE_SPTES 0x3f
- u8 pte[];
+ union nvkm_pte_tracker pte[];
};
typedef void (*nvkm_vmm_pxe_func)(struct nvkm_vmm *,