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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
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Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll_mgr.h')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dpll_mgr.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 6183da90b28d..5b71c860515f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -28,7 +28,6 @@
#include <linux/types.h>
#include "intel_display_power.h"
-#include "intel_wakeref.h"
#define for_each_dpll(__display, __pll, __i) \
for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \
@@ -42,6 +41,7 @@ struct intel_crtc_state;
struct intel_dpll_funcs;
struct intel_encoder;
struct intel_shared_dpll;
+struct ref_tracker;
/**
* enum intel_dpll_id - possible DPLL ids
@@ -255,6 +255,11 @@ struct intel_c20pll_state {
u16 mplla[10];
u16 mpllb[11];
};
+ struct intel_c20pll_vdr_state {
+ u8 custom_width;
+ u8 serdes_rate;
+ u8 hdmi_rate;
+ } vdr;
};
struct intel_cx0pll_state {
@@ -262,6 +267,7 @@ struct intel_cx0pll_state {
struct intel_c10pll_state c10;
struct intel_c20pll_state c20;
};
+ int lane_count;
bool ssc_enabled;
bool use_c10;
bool tbt_mode;
@@ -390,7 +396,7 @@ struct intel_dpll {
* @wakeref: In some platforms a device-level runtime pm reference may
* need to be grabbed to disable DC states while this DPLL is enabled
*/
- intel_wakeref_t wakeref;
+ struct ref_tracker *wakeref;
};
#define SKL_DPLL0 0
@@ -444,6 +450,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
const struct intel_dpll_hw_state *a,
const struct intel_dpll_hw_state *b);
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
+enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
void intel_dpll_state_verify(struct intel_atomic_state *state,