diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_device.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_device.h | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index b559ef43d547..13f2a629981f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -103,7 +103,9 @@ struct pci_dev; func(battlemage) \ /* Display ver 30 (based on GMD ID) */ \ func(pantherlake) \ - func(pantherlake_wildcatlake) + func(pantherlake_wildcatlake) \ + /* Display ver 35 (based on GMD ID) */ \ + func(novalake) #define __MEMBER(name) unsigned long name:1; @@ -147,7 +149,7 @@ struct intel_display_platforms { #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) -#define HAS_AUX_CCS(__display) (IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake) +#define HAS_AUX_DIST(__display) (IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake) #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display)) #define HAS_CASF(__display) (DISPLAY_VER(__display) >= 20) #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl) @@ -173,6 +175,7 @@ struct intel_display_platforms { #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) +#define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx) #define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg) #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3) #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake) @@ -185,10 +188,12 @@ struct intel_display_platforms { #define HAS_IPS(__display) ((__display)->platform.haswell_ult || (__display)->platform.broadwell) #define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12) #define HAS_LSPCON(__display) (IS_DISPLAY_VER(__display, 9, 10)) +#define HAS_LT_PHY(__display) ((__display)->platform.novalake) #define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14) #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12) #define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay) #define HAS_PIPEDMC(__display) (DISPLAY_VER(__display) >= 12) +#define HAS_PIXEL_NORMALIZER(__display) (DISPLAY_VER(__display) >= 35) #define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr) #define HAS_PSR_HW_TRACKING(__display) (DISPLAY_INFO(__display)->has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(__display) (DISPLAY_VER(__display) >= 12) @@ -197,9 +202,11 @@ struct intel_display_platforms { #define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \ BIT(trans)) != 0) #define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13) +#define HAS_UNDERRUN_DBG_INFO(__display) (DISPLAY_VER(__display) >= 35) #define HAS_ULTRAJOINER(__display) (((__display)->platform.dgfx && \ DISPLAY_VER(__display) == 14) && HAS_DSC(__display)) #define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11) +#define HAS_VRR_DC_BALANCE(__display) (DISPLAY_VER(__display) >= 30) #define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask)) #define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical) #define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv) @@ -255,6 +262,23 @@ struct intel_display_platforms { ((id) == ARLS_HOST_BRIDGE_PCI_ID3) || \ ((id) == ARLS_HOST_BRIDGE_PCI_ID4)) +#define INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe) \ + (DISPLAY_INFO((display))->pipe_offsets[(pipe)] - \ + DISPLAY_INFO((display))->pipe_offsets[PIPE_A] + \ + DISPLAY_MMIO_BASE((display))) + +#define INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans) \ + (DISPLAY_INFO((display))->trans_offsets[(trans)] - \ + DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \ + DISPLAY_MMIO_BASE((display))) + +#define INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe) \ + (DISPLAY_INFO((display))->cursor_offsets[(pipe)] - \ + DISPLAY_INFO((display))->cursor_offsets[PIPE_A] + \ + DISPLAY_MMIO_BASE((display))) + +#define DISPLAY_MMIO_BASE(display) (DISPLAY_INFO((display))->mmio_offset) + struct intel_display_runtime_info { struct intel_display_ip_ver { u16 ver; |