summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts')
-rw-r--r--arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts129
1 files changed, 127 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
index 2e39e7287730..b7ff7b8e1375 100644
--- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
@@ -12,6 +12,8 @@
model = "OpenWrt One";
aliases {
+ ethernet0 = &gmac1;
+ ethernet1 = &gmac0;
serial0 = &uart0;
};
@@ -67,9 +69,94 @@
linux,default-trigger = "netdev";
};
};
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&eth {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* WAN interface */
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ nvmem-cells = <&wan_factory_mac 0>;
+ nvmem-cell-names = "mac-address";
+ phy-mode = "2500base-x";
+ phy-handle = <&phy15>;
+ };
+
+ /* LAN interface */
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+ };
+};
+
+&mdio_bus {
+ phy15: ethernet-phy@f {
+ compatible = "ethernet-phy-id03a2.a411";
+ reg = <0xf>;
+ interrupt-parent = <&pio>;
+ interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+ airoha,pnswap-rx;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
};
&pio {
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_pereset";
+ };
+ };
+
pwm_pins: pwm-pins {
mux {
function = "pwm";
@@ -95,6 +182,22 @@
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
};
};
+
+ wifi_dbdc_pins: wifi-dbdc-pins {
+ mux {
+ function = "eth";
+ groups = "wf0_mode1";
+ };
+
+ conf {
+ pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
+ "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
+ "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
+ "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
+ "WF_CBA_RESETB", "WF_DIG_RESETB";
+ drive-strength = <4>;
+ };
+ };
};
&pwm {
@@ -112,8 +215,6 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
- #address-cells = <1>;
- #size-cells = <1>;
partitions {
compatible = "fixed-partitions";
@@ -160,6 +261,30 @@
};
};
+&sgmiisys0 {
+ mediatek,pnswap;
+};
+
&uart0 {
status = "okay";
};
+
+&usb_phy {
+ status = "okay";
+};
+
+&wifi {
+ nvmem-cells = <&wifi_factory_calibration>;
+ nvmem-cell-names = "eeprom";
+ pinctrl-names = "dbdc";
+ pinctrl-0 = <&wifi_dbdc_pins>;
+ status = "okay";
+};
+
+&xhci {
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ vusb33-supply = <&reg_3p3v>;
+ vbus-supply = <&reg_5v>;
+ mediatek,u3p-dis-msk = <0x01>;
+ status = "okay";
+};